EPSON  

800 x 600 Resolution 2 MB DRAM 64K Colors STN & TFT Display Controller

Mfr Part#: S1D13504F00A200
Packaging:  TRAY
Std Packaging Qty:  90

 
 
 

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$9.24 USD (each)
900+ $9.24 (Save 7%)

Availability

Qty in Stock : 0
Factory Stock : N/A
Factory Lead-Time: N/A
Min. Order Qty: 900
Multiple of: 90
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Overview

Product Highlight

  • Target LCD Panels: STN & TFT
  • Display Memory: 2 MB DRAM
  • Max Colors/Gray Scales: 64K Colors
  • Max Resolution: 800 x 600

The S1D13505 is a color/monochrome LCD/CRT graphics controller interfacing to a wide range of CPUs and display devices. The S1D13505 architecture is designed to meet the low cost, low power requirements of the embedded markets, such as Mobile Communications, Hand-Held PCs, and Office Automation.

The S1D13505 supports multiple CPUs, all LCD panel types, CRT, and additionally provides a number of
differentiating features. Products requiring a “Portrait” mode display can take advantage of the SwivelView feature. Simultaneous, Virtual and Split Screen Display are just some of the display modes supported, while the Hardware Cursor, Ink Layer, and the Memory Enhancement Registers offer substantial performance benefits. These features, combined with the S1D13505’s Operating System independence, make it an ideal display solution for a wide variety of applications.

Features:

  • Memory Interface:
    • 16-bit EDO-DRAM or FPM-DRAM interface
  • Memory size options:
    • 512K bytes using one 256K×16 device
    • 2M bytes using one 1M×16 device
  • Addressable as a single linear address space Display Support
  • 4/8-bit monochrome passive LCD interface
  • 4/8/16-bit color passive LCD interface
  • Single-panel, single-drive displays
  • Dual-panel, dual-drive displays
  • Direct support for 9/12-bit TFT/D-TFD; 18-bit TFT/D-TFD is supported up to 64K color depth (16-bit data)
  • Embedded RAMDAC with direct analog CRT drive
  • Simultaneous display of CRT and passive or TFT/D-TFD panels
  • Maximum resolution of 800x600 pixels at a color depth of 16 bpp
  • Clock Source:
    • Single clock input for both pixel and memory clocks
    • Memory clock can be input clock or (input clock/2),providing flexibility to use CPU bus clock as input.
    • Pixel clock can be memory clock or (memory clock/2) or (memory clock/3) or (memory clock/4)
  • Power Down Modes:
    • Software power save mode
    • LCD power sequencing General Purpose IO Pins
    • Up to 3 General Purpose IO pins are available
  • Operating Voltage:
    • 2.7 volts to 5.5 volts
  • Package:
    • 128-pin QFP15 surface mount package

Learn more about S1D13504F00A200 Display Controllers

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