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Référence fabricant

AS7C1026B-10TCN

AS7C1026B Series 1-Mbit (64 K x 16) 5 V 10 ns CMOS Static RAM - TSOP 11-44

Nom du fabricant: Alliance Memory
Emballage standard:
Product Variant Information section
Code de date: 1812
Product Specification Section
Caractéristiques techniques
Attributes Table
Memory Density: 1Mb
Memory Organization: 64 K x 16
Supply Voltage-Nom: 5V
Access Time-Max: 10ns
Temperature Grade: Commercial
Style d'emballage :  TSOP II-44
Méthode de montage : Surface Mount
Fonctionnalités et applications
The AS7C1026B is a high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized as 65,536 words × 16 bits. It is designed for memory applications where fast data access, low power, and simple interfacing are desired. Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5, 6, 7, 8 ns are ideal for high-performance applications.

When CE is high, the device enters standby mode. If inputs are still toggling, the device will consume ISB power. If the bus is static, then full standby power is reached (ISB1). For example, the AS7C1026B is guaranteed not to exceed 55 mW under nominal full standby conditions. A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O0 through I/O15 is written on the rising edge of WE (write cycle 1) or CE (write cycle 2).

To avoid bus contention, external devices should drive I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE). A read cycle is accomplished by asserting output enable (OE) and chip enable (CE) with write enable (WE) high. The chip drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive or write enable is active, output drivers stay in high-impedance mode.

The device provides multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and read. LB controls the lower bits, I/O0 through I/O7, and UB controls the higher bits, I/O8 through I/O15. All chip inputs and outputs are TTL-compatible, and operation is from a single 5 V supply. The device is packaged in common industry standard packages.

A 1MB 5.0V Fast Asynchronous Alliance product that has a 64K x16 configuration, with commercial temperature range (0˚C to 70˚C), and a 44-pin TSOP II package. The part supports 10 nanoseconds speeds and is RoHS compliant.
Pricing Section
Stock:
0
Commande minimale :
135
Multiples de :
135
Sur commande :Order inventroy details
12 783
Stock d'usine :Stock d'usine :
0
Délai d'usine :
N/A
Total 
292,95 $
USD
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$2.44
30
$2.24
100
$2.17
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$2.12
750+
$2.06
Product Variant Information section