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74HC Series 6 V 3-State Surface Mount Shift Register - SOIC-16

Modèle ECAD:
Nom du fabricant: Nexperia
Emballage standard:
Code de date: 2230
Product Specification Section
Nexperia 74HC595D,118 - Caractéristiques techniques
Attributes Table
Logic Circuit: Register
Family: A/HC/T/U
No of Functions / Channels: 1
Output Characteristics: 3-ST
Supply Voltage-Nom: 2V to 6V
Power Dissipation: 500mW
Propagation Delay: 16ns
Operating Temperature: -40°C to +125°C
Capacitance: 3.5pF
No of Inputs: 1
No of Outputs: Nine
High Level Output Current: -7.8mA
Low Level Output Current: 7.8mA
No of Pins: 16
Quiescent Current: 160µA
Moisture Sensitivity Level: 1
Style d'emballage :  SOIC-16
Méthode de montage : Surface Mount
$Fonctionnalités et applications
The first CMOS (Complementary Metal–Oxide–Semiconductor)  logic family of integrated circuits was introduced 1968. Initially CMOS logic was slower than LS-TTL; however, because the logic thresholds of CMOS were proportional to the power supply voltage, CMOS devices were well-adapted to battery-operated systems with simple power supplies.

Because of the incompatibility of the CD4000 series of chips with the previous TTL family, a new standard emerged which combined the best of the TTL family with the advantages of the CD4000 family. It was known as the 74HC (High performance silicon gate) family of devices.

With HC/HCT logic and LS-TTL logic competing in the market it became clear that a logic device that combined high speed, with low power dissipation and compatibility with older logic families was needed. A whole range of newer families has emerged that use CMOS technology.  Some of the more important family designators of these newer devices includes LV/LVT/ALVT.

The 74HC/HCT595 are high-speed Si-gate CMOSdevices and are pin compatible with low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A.

The 74HC/HCT595 is an 8-stage serial shift register with a storage register and 3-state outputs. The shift register and storage register have separate clocks.

Data is shifted on the positive-going transitions of the SH_CP input. The data in each register is transferred to the storage register on a positive-going transition of the ST_CP input. If both clocks are connected together, the shift register will always be one clock pulse ahead of the storage register.

The shift register has a serial input (DS) and a serial standard output (Q7?) for cascading. It is also provided with asynchronous reset (active LOW) for all 8 shift register stages. The storage register has 8 parallel 3-state bus driver outputs. Data in the storage register appears at the output whenever the output enable input (OE) is LOW.

The NXP 74HC595D-T is an 8-Bit CMOS Serial Shift Register with 3 State Output. It comes in a 16 Pin SOIC Tape and Reel Package.

Pricing Section
Stock globale:
282 500
d’Allemagne (En ligne seulement):
282 500
Sur commande :Order inventroy details
440 000
Stock d'usine :Stock d'usine :
Délai d'usine :
6 Semaines
Commande minimale :
Multiples de :
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