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Événement Électromécanique et Interconnexion

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Référence fabricant

M74VHC1GT125DT1G

74VHC Series SMT Single Non-Inverting Buffer / CMOS Logic Level Shifter TSOP-5

Modèle ECAD:
Nom du fabricant: onsemi
Emballage standard:
Product Variant Information section
Code de date:
Product Specification Section
onsemi M74VHC1GT125DT1G - Caractéristiques techniques
Attributes Table
Logic Circuit: Buffer
Family: A/VHC/T/U
No of Functions / Channels: 1
Supply Voltage-Nom: 3V to 5.5V
Style d'emballage :  SC-74A (TSOP-5, SOT-25)
Méthode de montage : Surface Mount
Fonctionnalités et applications

The MC74VHC1GT125 is a single gate noninverting buffer fabricated with silicon gate CMOS technology. It achieves high speed operation similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation. The MC74VHC1GT125 requires the 3-state control input (OE(bar)) to be set High to place the output into the high impedance state.

The device input is compatible with TTL-type input thresholds and the output has a full 5V CMOS level output swing. The input protection circuitry on this device allows overvoltage tolerance on the input, allowing the device to be used as a logic-level translator from 3.0V CMOS logic to 5.0V CMOS Logic or from 1.8V CMOS logic to 3.0V CMOS Logic while operating at the high-voltage power supply.

The MC74VHC1GT125 input structure provides protection when voltages up to 7V are applied, regardless of the supply voltage. This allows the MC74VHC1GT125 to be used to interface 5V circuits to 3V circuits. The output structures also provide protection when VCC = 0V. These input and output structures help prevent device destruction caused by supply voltage - input/output voltage mismatch, battery backup, hot insertion, etc.

Features:

  • High Speed: tPD = 3.5 ns (Typ) at VCC = 5 V
  • Low Power Dissipation: ICC = 1 µA (Max) at TA = 25°C
  • TTL−Compatible Inputs: VIL = 0.8 V; VIH = 2 V
  • CMOS−Compatible Outputs: VOH > 0.8 VCC; VOL < 0.1 VCC @Load
  • Power Down Protection Provided on Inputs and Outputs
  • Balanced Propagation Delays
  • Pin and Function Compatible with Other Standard Logic Families
  • Chip Complexity: FETs = 62; Equivalent Gates = 16
  • Pb−Free Packages are Available
Pricing Section
Stock global :
0
d’Allemagne (En ligne seulement):
0
Sur commande :Order inventroy details
63 000
Stock d'usine :Stock d'usine :
0
Délai d'usine :
15 Semaines
Commande minimale :
3000
Multiples de :
3000
Total 
206,40 $
USD
Quantité
Prix Internet
3 000
$0.0688
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$0.0671
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$0.0654
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$0.0648
45 000+
$0.0616
Product Variant Information section