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Référence fabricant

MC100EL34DG

MC100EL34 Series 1.1 GHz 5.7 V SMT ECL ÷2, ÷4, ÷8 Clock Generation Chip -SOIC-16

Modèle ECAD:
Nom du fabricant: onsemi
Emballage standard:
Product Variant Information section
Code de date:
Product Specification Section
Caractéristiques techniques
Attributes Table
Input Voltage-Max: 4120mV
Temperature Range: -40°C to +85°C
Supply Voltage-Nom: 4.2V to 5.7V
Frequency-Max: 1.1GHz
Style d'emballage :  SOIC-16
Méthode de montage : Surface Mount
Fonctionnalités et applications

The MC100EL34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 µF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.

The common enable (EN) is synchronous so that the internal dividers will only be enabled/disabled when the internal clock is already in the LOW state. This avoids any chance of generating a runt clock pulse on the internal clock when the device is enabled/disabled as can happen with an asynchronous control. An internal runt pulse could lead to losing synchronization between the internal divider stages. The internal enable flip−flop is clocked on the falling edge of the input clock, therefore, all associated specification limits are referenced to the negative edge of the clock input.

Upon startup, the internal flip-flops will attain a random state; the master reset (MR) input allows for the synchronization of the internal dividers, as well as multiple EL34s in a system. The 100 Series contains temperature compensation.

Key Features:

  • 50 ps Output-to-Output Skew
  • Synchronous Enable/Disable
  • Master Reset for Synchronization
  • PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V
  • NECL Mode Operating Range: VCC = 0 V with VEE = −4.2 V to −5.7 V
  • Internal Input 75 kΩ Pulldown Resistors on CLK(s), EN(Bar), and MR
  • Pb−Free Packages are Available

Learn more about the MC100EL3x Family of High Bandwidth

Pricing Section
Stock globale:
0
États-Unis:
0
Sur commande :
0
Stock d'usine :Stock d'usine :
5 760
Délai d'usine :
40 Semaines
Commande minimale :
96
Multiples de :
48
Total 
687,36 $
USD
Quantité
Prix Internet
48
$7.16
144
$6.15
240
$6.05
960
$5.80
1 440+
$5.73
Product Variant Information section