text.skipToContent text.skipToNavigation





Microchip Ethernet Transceivers (PHYs)

Designed specifically for today’s electronics applications

Microchip’s Ethernet PHYs are the industry’s first transceivers designed and validated to the new 10BASE-T1S standard for single-pair Ethernet released by IEEE. 10BASE-T1S addresses the challenges of creating all-Ethernet architectures for industrial applications such as process controls, building automation and consolidation of systems with multiple interconnection technologies. The configuration enables a multidrop (bus line) topology, fewer cables, development on printed circuit boards, with up to at least eight nodes and up to at least a 25-meter range.

LAN8670, LAN8671 and LAN8672

These three PHYs are compact, low power, and cost-effective single-port 10BASE-T1S Ethernet physical layer transceivers designed according to the IEEE Std 802.3cg-2019TM specification, providing 10 Mbit/s half-duplex transmit and receive capability over single-balanced pair medium such as Unshielded Twisted Pair (UTP) cable.

Designed for use in applications requiring an extended temperature range (-40°C to +125°C), the Microchip LAN867x transceivers are compliant to industrial EMC and EMI requirements.


The single-port Ethernet layer transceivers allow for the creation of both multidrop and point-to-point network topologies. Point-to-point link segments of up to at least 15m in length are supported. The multidrop mode supports up to at least 8 PHYs connected to a common mixing segment of up to at least 25m in length. The ability to connect multiple PHYs to a common mixing segment reduces weight and implementation costs by reducing cabling and switch ports.


Microchip Functional Safety Ready

High-performance 10BASE-T1S Ethernet PHY

Designed according to IEEE Std 802.3cg-2019™

  • 10 Mbit/s over single balanced pair
  • Half-duplex point-to-point link segments
  • Half-duplex multidrop mixing segments

Media Independent Interface (MII) with Serial Management Interface (SMI) for rapid register access

Carrier Sense Multiple Access / Collision Detection (CSMA/CD) media access control

Physical Layer Collision Avoidance (PLCA)

  • Allows for high bandwidth utilization by avoiding collisions on the physical layer
  • Burst mode for transmission of multiple packets for high packet rate latency-sensitive applications

Enhanced electromagnetic compatibility / electromagnetic interference (EMC/EMI) performance

Single 3.3V supply

Small footprint 36-pin VQFN packaging (6 x 6 mm) with wettable flanks

-40°C to +125°C extended temperature range