{"id":13712,"date":"2022-08-18T07:56:00","date_gmt":"2022-08-18T11:56:00","guid":{"rendered":"https:\/\/www.futureelectronics.com\/ftm\/?p=13712"},"modified":"2025-01-31T10:32:17","modified_gmt":"2025-01-31T15:32:17","slug":"running-real-time-applications-on-an-fpga-soc","status":"publish","type":"post","link":"https:\/\/www.futureelectronics.com\/ftm\/ai-edge-solutions\/running-real-time-applications-on-an-fpga-soc\/","title":{"rendered":"Future Electronics \u2014 Running Real-Time Applications on an FPGA SoC"},"content":{"rendered":"\t\t<div data-elementor-type=\"wp-post\" data-elementor-id=\"13712\" class=\"elementor elementor-13712\" data-elementor-post-type=\"post\">\n\t\t\t\t\t\t<section class=\"elementor-section elementor-top-section elementor-element elementor-element-79dacc25 elementor-section-content-middle elementor-section-height-min-height breadcrumbs elementor-hidden-phone elementor-section-boxed elementor-section-height-default elementor-section-items-middle\" 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elementor-element-populated\">\n\t\t\t\t\t\t<div class=\"elementor-element elementor-element-47c88ba6 elementor-widget elementor-widget-heading\" data-id=\"47c88ba6\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"heading.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t<h3 class=\"elementor-heading-title elementor-size-default\"><a href=\"https:\/\/www.futureelectronics.com\/ftm\/ai-edge-solutions\/\" rel=\"tag\">AI &amp; Edge Solutions<\/a><\/h3>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t<div class=\"elementor-column elementor-col-50 elementor-top-column elementor-element elementor-element-5f4c4b5a\" data-id=\"5f4c4b5a\" data-element_type=\"column\" data-e-type=\"column\">\n\t\t\t<div class=\"elementor-widget-wrap elementor-element-populated\">\n\t\t\t\t\t\t<div class=\"elementor-element elementor-element-35bbb45 elementor-nav-menu--stretch elementor-nav-menu--dropdown-tablet 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class=\"elementor-divider-separator\">\n\t\t\t\t\t\t<\/span>\n\t\t<\/div>\n\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<section class=\"elementor-section elementor-inner-section elementor-element elementor-element-21488313 elementor-section-boxed elementor-section-height-default elementor-section-height-default\" data-id=\"21488313\" data-element_type=\"section\" data-e-type=\"section\">\n\t\t\t\t\t\t<div class=\"elementor-container elementor-column-gap-no\">\n\t\t\t\t\t<div class=\"elementor-column elementor-col-50 elementor-inner-column elementor-element elementor-element-5368fd03\" data-id=\"5368fd03\" data-element_type=\"column\" data-e-type=\"column\">\n\t\t\t<div class=\"elementor-widget-wrap elementor-element-populated\">\n\t\t\t\t\t\t<div class=\"elementor-element elementor-element-60123d8 elementor-widget elementor-widget-global elementor-global-2759 elementor-widget-image\" data-id=\"60123d8\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"image.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<img decoding=\"async\" width=\"149\" height=\"53\" src=\"https:\/\/www.futureelectronics.com\/ftm\/wp-content\/uploads\/2025\/01\/FutureElectronicsWT-logo-resources-1.jpg\" class=\"attachment-full size-full wp-image-25195\" alt=\"\" \/>\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t<div class=\"elementor-column elementor-col-50 elementor-inner-column elementor-element elementor-element-64e3d7e\" data-id=\"64e3d7e\" data-element_type=\"column\" data-e-type=\"column\">\n\t\t\t<div class=\"elementor-widget-wrap\">\n\t\t\t\t\t\t\t<\/div>\n\t\t<\/div>\n\t\t\t\t\t<\/div>\n\t\t<\/section>\n\t\t\t\t<div class=\"elementor-element elementor-element-62e09b49 elementor-widget elementor-widget-heading\" data-id=\"62e09b49\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"heading.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t<h2 class=\"elementor-heading-title elementor-size-default\">Running Real-Time Applications on an FPGA SoC<\/h2>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-6da845c2 elementor-widget elementor-widget-heading\" data-id=\"6da845c2\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"heading.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t<h3 class=\"elementor-heading-title elementor-size-default\">Running real-time applications on an FPGA SoC:\nhow to design productively for a hybrid architecture\n<\/h3>\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-6a506275 elementor-widget elementor-widget-text-editor\" data-id=\"6a506275\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t\t\t<p><em>By Patrice Brossard<\/em><\/p><p><em>EMEA Vertical Segment Manager (FPGAs and ASICs), Future Electronics <\/em><\/p><p>\u00a0<\/p><p>The inexorable progress of integration in semiconductors has been blurring the boundaries between different types of components for many years. By loading up one type of component with IP from a different kind, a sensor can become a machine learning inference engine, a microcontroller can be made to behave like an applications processor, or a non-volatile memory can provide a secure hardware root-of-trust.<\/p><p>\u00a0<\/p><p>Late in 2019, this blurring took another step forward with the merging of two types of system which have almost completely different sets of attributes: an FPGA, and processors running real-time applications in a Linux\u00ae operating environment. An FPGA is a programmable hardware fabric which supports the parallel processing of multiple concurrent tasks, while a processor is a hardware platform for executing a fixed instruction set architecture (ISA), and supports the serial processing of threads of instructions.<\/p><p>\u00a0<\/p><p>The 2019 introduction of the Microchip PolarFire\u00ae SoC FPGA bolted together these two component types, creating a single system-on-chip which provides:<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-a3d097f elementor-widget elementor-widget-text-editor\" data-id=\"a3d097f\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t\t\t<ul><li>The resources expected of a mid-density FPGA, including up to 461k logic elements, up to 1,420 18&#215;18 math blocks, up to 33 Mbits of user SRAM, eight fully configurable PLLs, a high-speed DDR4 interface capability up to 1.6 Gbits\/s, and multi-protocol transceivers operating at a data rate of up to 12.7 Gbits\/s with two hard-wired PCIe Gen2 end-points\/root ports. Fabricated on a mature, low-power SONOS 28 nm process, it can achieve remarkably low power consumption.<\/li><li>A multi-core applications processor consisting of a quad-core 64-bit RISC-V core cluster, and a separate 64-bit RISC-V monitor core. All five cores operate at a speed of up to 625 MHz. The direct processor I\/O capabilities include two Gigabit Ethernet controllers, a USB 2.0 On-The-Go controller and two CAN interfaces.<\/li><\/ul>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-26ba7b4 elementor-widget elementor-widget-text-editor\" data-id=\"26ba7b4\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t\t\t<p>This means that electronics system architects now have the option of using a single chip which offers both the low power consumption, high thermal efficiency and defense-grade security of an FPGA, and the deterministic execution capabilities provided by a fast processor.<\/p><p>\u00a0<\/p><p>This hybrid architecture clearly requires a system design engineering team to straddle the two worlds of the FPGA and the microprocessor. So what are the challenges involved in integrating these two types of hardware system into a single, reliable end product design? This hybrid SoC platform offers unique capabilities and advantages in applications such as systems operating in environments subject to extreme temperatures, artificial intelligence (AI) inferencing at the edge, security-conscious applications, aerospace and defense systems, and communications infrastructure. But is the difficulty of combining these two product types worth accepting to gain these advantages?<\/p><p>\u00a0<\/p><p><strong>Understanding the hybrid processor\/FPGA architecture <\/strong><\/p><p>At the heart of the PolarFire SoC FPGA is a deterministic, coherent CPU cluster of 4+1 RISC-V cores, as shown in Figure 1. RISC-V is a free and open functional specification for a processor\u2019s ISA, and is backed by a growing ecosystem of development professionals, specifications, software and other resources.<\/p><p>\u00a0<\/p><p>For the CPU cluster in the PolarFire SoC, Microchip has developed its own hardware architecture in collaboration with RISC-V specialist SiFive. A unique feature of the Microchip implementation is the freedom to turn off CPU branch prediction and make the memory sub-system fully deterministic.<\/p><p>\u00a0<\/p><p>This eliminates all variation in execution time while maintaining the high processor performance provided by the four RISC-V cores, and also making use of the deterministic features of the PolarFire FPGA.<\/p><p>\u00a0<\/p><p>The fifth core, a monitor core, is used to manage the boot process and system configuration. Unlike the application processing cores, it does not include virtual memory support.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-0968bec elementor-widget elementor-widget-image\" data-id=\"0968bec\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"image.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<img loading=\"lazy\" decoding=\"async\" width=\"800\" height=\"558\" src=\"https:\/\/www.futureelectronics.com\/ftm\/wp-content\/uploads\/2022\/08\/FE-FPGA-SoC-Fig-01.jpg\" class=\"attachment-large size-large wp-image-13713\" alt=\"Future Electronics \u2014 Running Real-Time Applications on an FPGA SoC\" srcset=\"https:\/\/www.futureelectronics.com\/ftm\/wp-content\/uploads\/2022\/08\/FE-FPGA-SoC-Fig-01.jpg 900w, https:\/\/www.futureelectronics.com\/ftm\/wp-content\/uploads\/2022\/08\/FE-FPGA-SoC-Fig-01-300x209.jpg 300w, https:\/\/www.futureelectronics.com\/ftm\/wp-content\/uploads\/2022\/08\/FE-FPGA-SoC-Fig-01-768x536.jpg 768w\" sizes=\"(max-width: 800px) 100vw, 800px\" \/>\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-9f964d8 elementor-widget elementor-widget-text-editor\" data-id=\"9f964d8\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t\t\t<p><em>Fig. 1: The PolarFire SoC architecture combines separate FPGA hardware and a CPU cluster. (Image credit: Microchip)<\/em><\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-c1fe7b2 elementor-widget elementor-widget-text-editor\" data-id=\"c1fe7b2\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t\t\t<p>\u00a0<\/p><p>All the SoC\u2019s memories feature ECC with single error detection, providing a very high level of data integrity, which is a mandatory requirement in safety-critical applications, for instance in aerospace systems.<\/p><p>\u00a0<\/p><p>A hallmark of the PolarFire SoC FPGA is its very low power consumption: Figure 2 shows a comparison of the PolarFire SoC\u2019s power usage as a function of CoreMark\u00ae processor loading against that of traditional Arm\u00ae Cortex\u00ae-A microprocessor cores.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-ab24858 elementor-widget elementor-widget-image\" data-id=\"ab24858\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"image.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<img loading=\"lazy\" decoding=\"async\" width=\"800\" height=\"509\" src=\"https:\/\/www.futureelectronics.com\/ftm\/wp-content\/uploads\/2022\/08\/FE-FPGA-SoC-Fig-02-1024x652.jpg\" class=\"attachment-large size-large wp-image-13719\" alt=\"Future Electronics \u2014 Running Real-Time Applications on an FPGA SoC\" srcset=\"https:\/\/www.futureelectronics.com\/ftm\/wp-content\/uploads\/2022\/08\/FE-FPGA-SoC-Fig-02-1024x652.jpg 1024w, https:\/\/www.futureelectronics.com\/ftm\/wp-content\/uploads\/2022\/08\/FE-FPGA-SoC-Fig-02-300x191.jpg 300w, https:\/\/www.futureelectronics.com\/ftm\/wp-content\/uploads\/2022\/08\/FE-FPGA-SoC-Fig-02-768x489.jpg 768w, https:\/\/www.futureelectronics.com\/ftm\/wp-content\/uploads\/2022\/08\/FE-FPGA-SoC-Fig-02.jpg 1200w\" sizes=\"(max-width: 800px) 100vw, 800px\" \/>\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-d2c5c6d elementor-widget elementor-widget-text-editor\" data-id=\"d2c5c6d\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t\t\t<p><em>Fig. 2: Comparison of power consumption between the PolarFire SoC and Arm Cortex-A microprocessor cores. (Image credit: Microchip)<\/em><\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-f8b5f1e elementor-widget elementor-widget-text-editor\" data-id=\"f8b5f1e\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t\t\t<p>This is clearly advantageous in battery-powered systems, but not only there: in any system, low power consumption can eliminate the need for a heat-sink or fan, reducing system cost, size and weight, and improving its reliability.<\/p><p>\u00a0<\/p><p><strong>Memory partition supports real-time Linux operation <\/strong><\/p><p>Alongside the mid-density FPGA portion of the PolarFire SoC, Microchip has also implemented an architecture which provides a real-time deterministic multi-processing capability. To run operating system (OS) software on a multi-core system, an MPU manufacturer can choose one of two types of multi-processing architecture:<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-f17a00c elementor-widget elementor-widget-text-editor\" data-id=\"f17a00c\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t\t\t<ul><li>In symmetric multi-processing (SMP), all the cores will share the main memory. The cores in SMP are homogeneous, and the OS treats each one equally. This architecture enables the manufacturer to increase the performance of a single-core device by adding identical cores<\/li><li>In asymmetric multi-processing (AMP), the OS treats cores differently, and they do not share the same memory and peripherals. This allows the system designer to assign certain kinds of tasks to one core, while leaving another core free to run the OS, for example<\/li><\/ul>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-83a8c9a elementor-widget elementor-widget-text-editor\" data-id=\"83a8c9a\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t\t\t<p>Certain features of a typical SMP architecture, such as branch prediction and cache misses, make it impossible for the SoC to operate deterministically. Execution time is inconsistent and cannot be guaranteed because every core is exposed to periodic interrupts.<\/p><p>\u00a0<\/p><p>By contrast, the AMP implementation allows the developer to carve out a part of the cache memory, and reserve it for use exclusively by a real-time application. The PolarFire SoC supports both SMP and AMP modes, providing the developer with the freedom to choose one or the other, and even to change modes during field updates.<\/p><p>\u00a0<\/p><p>Once the AMP mode is configured in the PolarFire SoC, the real-time application can run on one of the application cores, a real-time core in which branch prediction has been turned off, as shown in Figure 3.<\/p><p>\u00a0<\/p><p>This hardware structure supports the fully deterministic operation of real-time functions alongside the Linux OS. In addition, interrupt service routing (ISR) execution times are deterministic, a claim which cannot be made as confidently for an SMP architecture implemented on an equivalent quad-core microprocessor based on Arm Cortex-A technology. <\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-22337bf elementor-widget elementor-widget-image\" data-id=\"22337bf\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"image.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<img loading=\"lazy\" decoding=\"async\" width=\"800\" height=\"425\" src=\"https:\/\/www.futureelectronics.com\/ftm\/wp-content\/uploads\/2022\/08\/FE-FPGA-SoC-Fig-03-1024x544.jpg\" class=\"attachment-large size-large wp-image-13725\" alt=\"Future Electronics \u2014 Running Real-Time Applications on an FPGA SoC\" srcset=\"https:\/\/www.futureelectronics.com\/ftm\/wp-content\/uploads\/2022\/08\/FE-FPGA-SoC-Fig-03-1024x544.jpg 1024w, https:\/\/www.futureelectronics.com\/ftm\/wp-content\/uploads\/2022\/08\/FE-FPGA-SoC-Fig-03-300x159.jpg 300w, https:\/\/www.futureelectronics.com\/ftm\/wp-content\/uploads\/2022\/08\/FE-FPGA-SoC-Fig-03-768x408.jpg 768w, https:\/\/www.futureelectronics.com\/ftm\/wp-content\/uploads\/2022\/08\/FE-FPGA-SoC-Fig-03.jpg 1200w\" sizes=\"(max-width: 800px) 100vw, 800px\" \/>\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-aacb62d elementor-widget elementor-widget-text-editor\" data-id=\"aacb62d\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t\t\t<p><em>Fig. 3: In the PolarFire SoC AMP architecture, real-time functions access a dedicated portion of the L2 cache memory directly. (Image credit: Microchip)<\/em><\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-edc9474 elementor-widget elementor-widget-text-editor\" data-id=\"edc9474\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t\t\t<p><strong>Mastering hybrid FPGA\/MPU system design<\/strong><\/p><p>A hybrid FPGA\/MPU SoC offers a unique ability to meet the requirements of certain kinds of application with a single chip. An application which concurrently performs local inferencing based on a machine learning model, and controls in real time the operation of a safety-critical motor, for instance, can implement the AI functions in the PolarFire SoC\u2019s FPGA and the safety-critical controls on the multi-core processor.<\/p><p>\u00a0<\/p><p>The presence of both an FPGA and an MPU on the same chip, however, means that the system design team has to work in two independent design environments. Both the PolarFire SoC\u2019s toolchains feed into a configurator which generates:<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-9152264 elementor-widget elementor-widget-text-editor\" data-id=\"9152264\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t\t\t<ul><li>The \u2018software\u2019 configuration: the C data structures for initializing the memory map, which will be used in the SoftConsole\u00ae integrated development environment (IDE)<\/li><li>The \u2018hardware\u2019 configuration: a so-called component, which will be used in the Libero FPGA IDE<\/li><\/ul>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-23013f7 elementor-widget elementor-widget-text-editor\" data-id=\"23013f7\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t\t\t<p>The interaction between the two IDEs is shown in Figure 4.<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-2f97dd3 elementor-widget elementor-widget-image\" data-id=\"2f97dd3\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"image.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<img loading=\"lazy\" decoding=\"async\" width=\"800\" height=\"284\" src=\"https:\/\/www.futureelectronics.com\/ftm\/wp-content\/uploads\/2022\/08\/FE-FPGA-SoC-Fig-04-1024x364.jpg\" class=\"attachment-large size-large wp-image-13731\" alt=\"Future Electronics \u2014 Running Real-Time Applications on an FPGA SoC\" srcset=\"https:\/\/www.futureelectronics.com\/ftm\/wp-content\/uploads\/2022\/08\/FE-FPGA-SoC-Fig-04-1024x364.jpg 1024w, https:\/\/www.futureelectronics.com\/ftm\/wp-content\/uploads\/2022\/08\/FE-FPGA-SoC-Fig-04-300x107.jpg 300w, https:\/\/www.futureelectronics.com\/ftm\/wp-content\/uploads\/2022\/08\/FE-FPGA-SoC-Fig-04-768x273.jpg 768w, https:\/\/www.futureelectronics.com\/ftm\/wp-content\/uploads\/2022\/08\/FE-FPGA-SoC-Fig-04.jpg 1500w\" sizes=\"(max-width: 800px) 100vw, 800px\" \/>\t\t\t\t\t\t\t\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-e00e6d4 elementor-widget elementor-widget-text-editor\" data-id=\"e00e6d4\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t\t\t<p><em>Fig. 4: The relationship between the Libero IDE for the FPGA and the SoftConsole IDE for the MPU. (Image credit: Microchip)<\/em><\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-13596f4 elementor-widget elementor-widget-text-editor\" data-id=\"13596f4\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t\t\t<p>\u00a0<\/p><p>Design simulation is also supported by separate tools: Renode for the software running on the multi-core processor part, and ModelSim for the FPGA part of the SoC. Microchip has also made good provision for debugging the complex applications which will run on the PolarFire SoC. Its on-chip-debugging mechanism communicates through a JTAG interface to debug tools:<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-b876910 elementor-widget elementor-widget-text-editor\" data-id=\"b876910\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t\t\t<ul><li>C code can be debugged using a traditional openOCD debugger<\/li><li>The FPGA debug tool is more specialized, as a debug mechanism is embedded by default in the component to give access to any internal node of the FPGA matrix dynamically. A dedicated tool, Smartdebug, uses this internal debugging circuitry to provide an intuitive means to debug the FPGA-based part of the application<\/li><\/ul>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-581bd50 elementor-widget elementor-widget-text-editor\" data-id=\"581bd50\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t\t\t<p>Interestingly, the conditions for porting an application to the RISC-V environment are similar to those applying within the Arm environment. No two Arm core-based devices will have the same memory map, and equally no two RISC-V-based systems will share the same memory map. So porting from one Arm core to another requires in principle the same effort as porting from an Arm core to a RISC-V core.<\/p><p>\u00a0<\/p><p><strong>A design-friendly operating and development environment<\/strong><\/p><p>The PolarFire SoC, then, offers the advantage of integrating in a single chip both programmable hardware capabilities and a high-performance, multi-core platform for software applications. This hybrid architecture does entail the use of two development environments in parallel, but Microchip has taken great care to provide the user with a comprehensive set of tools which are extremely well integrated, and provide the capability for design teams to work productively in:<\/p>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-b742113 elementor-widget elementor-widget-text-editor\" data-id=\"b742113\" data-element_type=\"widget\" data-e-type=\"widget\" data-widget_type=\"text-editor.default\">\n\t\t\t\t<div class=\"elementor-widget-container\">\n\t\t\t\t\t\t\t\t\t<ul><li>Creating or migrating the system<\/li><li>Simulating the design<\/li><li>Programming both the hardware resources in the FPGA portion of the chip, and application software running on the processor cluster<\/li><li>Debugging the system<\/li><\/ul>\t\t\t\t\t\t\t\t<\/div>\n\t\t\t\t<\/div>\n\t\t\t\t<div class=\"elementor-element elementor-element-bba46c7 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architecture.<\/p>\n","protected":false},"author":1,"featured_media":13737,"comment_status":"closed","ping_status":"open","sticky":false,"template":"elementor_header_footer","format":"standard","meta":{"footnotes":""},"categories":[139],"tags":[169],"class_list":["post-13712","post","type-post","status-publish","format-standard","has-post-thumbnail","hentry","category-ai-edge-solutions","tag-issue-6-2022"],"yoast_head":"<!-- This site is optimized with the Yoast SEO Premium plugin v27.1 (Yoast SEO v27.3) - https:\/\/yoast.com\/product\/yoast-seo-premium-wordpress\/ -->\n<title>Future Electronics \u2014 Running Real-Time Applications on an FPGA SoC &#8211; Future Technology Magazine<\/title>\n<meta name=\"robots\" content=\"index, follow, max-snippet:-1, max-image-preview:large, max-video-preview:-1\" \/>\n<link rel=\"canonical\" href=\"https:\/\/www.futureelectronics.com\/ftm\/ai-edge-solutions\/running-real-time-applications-on-an-fpga-soc\/\" \/>\n<meta property=\"og:locale\" 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