ATSAME54 SAM E54 Xplained Pro 32-Bit Embedded Evaluation Board
ERRATA - SAM D5x/E5x Family Errata and Data Sheet ClarificationMicrochip has released a new DeviceDoc for the SAM D5x/E5x Family Errata and Data Sheet Clarification of devices.Notification Status: FinalDescription of Change:The following silicon issues were added:1) SERCOM I2C - 2.18.16 SERCOM I2C: Repeated Start2) CAN-FD - 2.4.3 Message Transmitted with Wrong Arbitration and Control Fields - 2.4.4 DAR Mode - 2.4.5 High-Priority Message (HPM) interrupt - 2.4.6 Tx FIFO message sequence inversion3) PDEC - 2.22.1 X2 Mode4) DMAC - 2.10.2 Channel Priority - 2.10.3 DMAC in Debug Mode5) RTC - 2.17.2 COUNTSYNC - 2.17.3 Tamper Input Filter - 2.17.4 Tamper Detection - 2.17.5 Tamper Detection Timestamp6) SUPC - 2.19.2 BOD33 Hysteresis7) TCC - 2.21.3 ALOCK Feature - 2.21.4 LUPD feature in Down-Counting ModeThe following Data Sheet Clarifications were added:1) Table 54-35 Flash Timing Characteristics was updated.2) BOD12 Register Information was updatedImpacts to Data Sheet: NoneReason for Change: To Improve ProductivityChange Implementation Status: CompleteDate Document Changes Effective: 23 Nov 2018NOTE: Please be advised that this is a change to the document only the product has not been changed.Markings to Distinguish Revised from Unrevised Devices: N/A
Data Sheet - SAM D5X/E5X Family Datasheet Data Sheet Document RevisionNotification Status: FinalDescription of Change:1) Added ordering information for 105°C and 125°C temperature grade.2) Exposed pad info added for QFN package in Pinout section3) Corrected typographical errors for pin numbers PB19 and PB23 in I/O Multiplexing and Considerations section4) Clarified NVM User Page size in table 9-1.5) Corrected typographical errors in section 10.2.2 Interrupt Line Mapping for SERCOMx interrupt line 7.6) Corrected typographical errors related to R/W bits for 15.8.8 APBA Mask Register7) Updated Figure 18-2 Operating Conditions and SleepWalking to reflect that PL0 is not applicable to this product.8) Updated INTENCLR, INTENSET, INTFLAG, and STATUS Registers to reflect factory preprogramming of BOD12.9) Removed CHIP.ID information as it is not applicable to this product in DMAC section10) Corrected typographical errors in the USERm Register offset.11) In CCL section1. Internal Events Inputs Selection (EVENT) section was updated by removing ASYNCEVENT related information.2. Alternate 2 TC input source not applicable and was removed for LUTCTRL.INSELx bits.12) Added clarification for INTREF to 45.8.6 Reference Control(REFCTRL).13) In TC section1. 48.7.1 Register Summary - 8-bit Mode - Updated register bitfield with indexing to display usage.2. 48.7.2 Register Summary - 16-bit Mode2.1. Updated register bitfield with indexing to display usage.2.2. Removed inapplicable register PER & PERBUF register information.3. 48.7.3 Register Summary - 32-bit Mode3.1. Updated register bitfield with indexing to display usage.3.2. Removed inapplicable register PER & PERBUF register information.14) In TCC - Timer/Counter for Control Applications section1. Table 49-4. Output Matrix Channel Pin Routing Configuration updated to show all supported 6 capture channels.2. Table 49-8. Fault and Capture Action updated by adding missing CAPTMARK value for CAPTURE bit fields.3. Register INTENCLR, INTENSET, INTFLAG updated with missing UFS bit.4. Removed unsupported bit info for the register 49.8.15 Pattern (PATT).5. Missing POLx bits added to the register 49.8.16 Waveform (WAVE).6. 49.7 Register Summary - Updated register bitfield with indexing to display usage.15) In 54. Electrical Characteristics at 85°C section1. Clarified how CLEXT can be computed in section 54.12.1 Crystal Oscillator (XOSC) Characteristics and 54.12.2 External 32 kHz Crystal Oscillator (XOSC32K) Characteristics2. Clarified capacitor requirements in Table 54-18. External Components Requirements in Switching Mode and Table 54-19 Decoupling Requirements.3. Condition shown for VREF parameter is removed in table 54-24. Operating Conditions.4. Conditions specified for table 54-29 Differential Mode is clarified for INL & DNL with Internal voltage reference.5. Table 54-35. Flash Timing Characteristics is updated for Chip Erase maximum time.6. Added the missing note in Table 54-44. UltraLow-Power Internal 32kHz Oscillator Electrical Characteristics.7. Added the missing note in Table 54-48. Fractional Digital Phase Lock Loop Characteristics8. Typo for the maximum value of tMOH in the Table 54-51. SPI Timing Characteristics and Requirements addressed.9. Table 54-53. QSPI Maximum Frequency examples updated.16) Introduced device part numbers with Electrical Characteristics for 105°C temperature grade.17) Introduced device part numbers with Electrical Characteristics for 125°C temperature gradeImpacts to Data Sheet: NoneReason for Change: To Improve ProductivityChange Implementation Status: CompleteEstimated First Ship Date: 23 Nov 2018NOTE: Please be advised that this is a change to the document only the product has not been changed.
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