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Manufacturer Part #

74HC109D,653

74HC Series 6 V SMT Dual JK Flip-Flop with Set and Reset - SOIC-16

ECAD Model:
Mfr. Name: Nexperia
Standard Pkg:
Product Variant Information section
Date Code:
Product Specification Section
Technical Attributes
Attributes Table
Logic Circuit: Flip-Flop
Family: A/HC/T/U
No of Functions / Channels: 2
Output Characteristics: Differential
Supply Voltage-Nom: 2V to 6V
Power Dissipation: 0.5W
Propagation Delay: 14ns
Operating Temperature: -40°C to +125°C
Capacitance: 3.5pF
No of Inputs: 4
No of Outputs: Dual
High Level Output Current: -5.2mA
Low Level Output Current: 5.2mA
No of Pins: 16
Quiescent Current: 4µA
Moisture Sensitivity Level: 1
Package Style:  SOIC-16
Mounting Method: Surface Mount
Features & Applications

The 74HC109D are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL).  The 74HC109 are dual positive-edge triggered, JK flip-flops with individual J, K inputs, clock (CP) inputs, set (SD ) and reset (RD ) inputs; also complementary Q and Q outputs.

The set and reset are asynchronous active LOW inputs and operate independently of the clock input. The J and K inputs control the state changes of the flip-flops as described in the mode select function table. The J and K inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition for predictable operation.

Features:

  • J, K inputs for easy D-type flip-flop
  • Toggle flip-flop or "do nothing" mode
  • Output capability: standard
  • ICC category: flip-flops

 

 

Pricing Section
Global Stock:
0
USA:
0
On Order:
0
Factory Stock:Factory Stock:
0
Factory Lead Time:
52 Weeks
Minimum Order:
7500
Multiple Of:
2500
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Tariff charges may apply if shipping to the United States. An estimate of tariff charges will be calculated at checkout.
Total
$2,062.50
USD
Quantity
Web Price
2,500
$0.305
5,000
$0.29
7,500
$0.275
10,000+
$0.26
Product Variant Information section