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Manufacturer Part #

74LVC74APW,118

74LVC Series 3.6 V SMT Positive Edge Trigger Dual D-Type Flip Flop - TSSOP-14

Product Specification Section
Technical Attributes
Attributes Table
Logic Circuit: D-Type, Flip Flop IC
Family: A/LVC/E/H/U
No of Functions / Channels: 2
Output Characteristics: Complementary
Supply Voltage-Nom: 1.65V to 3.6V
Power Dissipation: 0.5W
Propagation Delay: 2.6ns
Operating Temperature: -40°C to +125°C
Capacitance: 4pF
No of Inputs: 2
No of Outputs: Dual
High Level Output Current: -24mA
Low Level Output Current: 24mA
No of Pins: 14
Quiescent Current: 0.1µA
Moisture Sensitivity Level: 1
Package Style:  TSSOP-14
Mounting Method: Surface Mount
Features & Applications

The 74LVC74APW is a dual edge triggered D-type flip-flop with individual data (D) inputs, clock (CP) inputs, set (SD) and (RD) inputs, and complementary Q and Q outputs.

The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D inputs must be stable one set-up time prior to the LOW-to-HIGH clock transition, for predictable operation.

Features:

  • 5 V tolerant inputs for interlacing with 5 V logic
  • Wide supply voltage range from 1.2 V to 3.6 V
  • CMOS low power consumption
  • Direct interface with TTL levels
  • Complies with JEDEC standard JESD8-B/JESD36
  • ESD protection:
    • HBM JESD22-A114D exceeds 2000 V
    • CDM JESD22-C101C exceeds 1000 V
  • Specified from -40 Cel to +85 Cel and -40 Cel to 125 Cel

 

 

 
Pricing Section
Stock:
7,500
Minimum Order:
2,500
Multiple Of:
2,500
475,000
Factory Stock:Factory Stock:
0
Total
$201.25
USD
Quantity
Web Price
2,500
$0.0805
5,000
$0.0672
10,000
$0.0662
12,500
$0.0659
37,500+
$0.0644