Manufacturer Part #
CY7C1011DV33 Series 2 Mb (128 K x 16) 3.3 V 10 ns Static RAM - VFBGA-48
|Standard Pkg:|| |
Product Variant Information section
480 per Tray
Addendum to PIN195102 - Manufacturing Label and Packing Configuration Standardization Description of Change: The purpose of this addendum is to correct the date from January 20, 2019 to January 20, 2020, in the "3rd paragraph in the 'Description of Change' section. This notification is to inform customers that Cypress will be standardizing its manufacturing labels and tray/tube packing configuration. It may be recalled that the Cypress entity consolidation (following the merger with Spansion Corp) was announced via Product Information Notification PIN174801 in November 2017. As the next phase of the entity consolidation process, Cypress will be adapting a new manufacturing label format for all products and revising shipping configurations for select product shipped in trays and tubes.
Planned Qualification of Spansion Manufacturing Sites for Cypress ProductsDescription of Change:In concert with the recently announced merger between Cypress Semiconductor Corporation (Cypress) and Spansion Inc. (Spansion), Cypress announces plans to qualify proprietary SONOS Technology products at Spansion Fab 25 / Test 25 in Austin, Texas and BGA/TSOP-packaged products at the Spansion assembly facility in Bangkok, Thailand. These qualifications and implementations are expected to occur throughout 2015 and 2016. Once complete, the qualifications will be announced through regular PCNs.This is an advance notification and no immediate action is needed. Refer to the attached Supplier documentation for the complete schedule of the activity, PCN issue dates and shipment start dates.
|Memory Organization:||128 K x 16|
|Mounting Method:||Surface Mount|
Features & Applications
The CY7C1011DV33 is a high-performance CMOS Static RAM organized as 128 K words by 16 bits. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0 through A16). If Byte High Enable (BHE) is LOW, then data from I/O pins (I/O8 through I/O15) is written into the location specified on the address pins (A0 through A16).
The CY7C1011DV33 is available in standard Pb-free 44-pin TSOP II with center power and ground pinout, as well as 48-ball very fine-pitch ball grid array (VFBGA) packages.
- Pin-and function-compatible with CY7C1011CV33
- High speed
- tAA = 10 ns
- Low active power
- ICC = 90 mA @ 10 ns (Industrial)
- Low CMOS standby power
- ISB2 = 10 mA
- Data Retention at 2.0 V
- Automatic power-down when deselected
- Independent control of upper and lower bits
- Easy memory expansion with CE and OE features
- Available in Pb-free 44-pin TSOP II, and 48-ball VFBGA
480 per Tray