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Manufacturer Part #

CY7C1312KV18-300BZXI

CY7C1312KV18 Series 18 Mb (1 M x 18) 1.8 V Static RAM - FBGA-165

ECAD Model:
Mfr. Name: Cypress
Standard Pkg:
Product Variant Information section
Date Code:
Product Specification Section
Technical Attributes
Attributes Table
Memory Density: 18Mb
Memory Organization: 1 M x 18
Supply Voltage-Nom: 1.8V
Package Style:  FBGA-165
Mounting Method: Surface Mount
Features & Applications

The CY7C1312KV18-300BZXI is a 1.8 V Synchronous pipelined SRAM organized as 1M x 18 bits, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port to access the memory array.

The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations.

Features:

  • Separate independent read and write data ports
    • Supports concurrent transactions
  • 333 MHz clock for high bandwidth
  • Two-word burst on all accesses
  • Double-data rate (DDR) interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz
  • Two input clocks (K and K) for precise DDR timing
    • SRAM uses rising edges only
  • Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches
  • Echo clocks (CQ and CQ) simplify data capture in high-speed systems
  • Single multiplexed address input bus latches address inputs for both read and write ports
  • Separate port selects for depth expansion
  • Synchronous internally self-timed writes
  • QDR® II operates with 1.5 cycle read latency when DOFF is asserted HIGH
  • Operates similar to QDR I device with one cycle read latency when DOFF is asserted LOW
  • Available in × 18, and × 36 configurations
  • Full data coherency, providing most current data
  • Core VDD = 1.8 V (±0.1 V); I/O VDDQ = 1.4 V to VDD
    • Supports both 1.5 V and 1.8 V I/O supply
  • Available in 165-ball FBGA package (13 × 15 × 1.4 mm)
  • Offered in both Pb-free and non Pb-free packages
  • Variable drive HSTL output buffers
  • JTAG 1149.1 compatible test access port
  • PLL for accurate data placement
Pricing Section
Global Stock:
0
USA:
0
On Order:
0
Factory Stock:Factory Stock:
0
Factory Lead Time:
42 Weeks
Minimum Order:
136
Multiple Of:
136
Total
$4,701.52
USD
Quantity
Web Price
136+
$34.57
Product Variant Information section