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Manufacturer Part #

CY7C1315KV18-250BZXC

CY7C1315KV18 Series 18 Mb (512 K x 36) 1.7 - 1.9 V QDR® II SRAM - FBGA-165

ECAD Model:
Mfr. Name: Cypress
Standard Pkg:
Product Variant Information section
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Product Specification Section
Technical Attributes
Attributes Table
Memory Density: 18Mb
Memory Organization: 512 K x 36
Supply Voltage-Nom: 1.7V to 1.9V
Access Time-Max: 0.45ns
Temperature Grade: Commercial
Speed: 250MHz
Number of Words: 512 K
Word Length: 36b
Supply Current: 590mA
Interface Circuit Type: Parallel
Operating Temp Range: 0°C to 70°C
Storage Temperature Range: -65°C to +150°C
Moisture Sensitivity Level: 3
Package Style:  FBGA-165
Mounting Method: Surface Mount
Features & Applications

The CY7C1315KV18-250BZXC is a part of CY7C1315KV18 series 1.7 - 1.9 V 18 Mbit (512 K x 36) QDR® II SRAM available in a FBGA-165 package.

This series are of 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port. QDR II architecture has separate data inputs and data outputs to completely eliminate the need to ‘turnaround’ the data bus that exists with common I/O devices.

Product Features:

  • Separate independent read and write data ports
  • Supports concurrent transactions
  • 333-MHz clock for high bandwidth
  • Four-word burst for reducing address bus frequency
  • Double data rate (DDR) interfaces on both read and write ports (data transferred at 666 MHz) at 333 Hz
  • Two input clocks (K and K) for precise DDR timing
  • SRAM uses rising edges only
  • Two Input Clocks for Output Data (C and C) to minimize Clock skew and flight time mismatches
  • Echo clocks (CQ and CQ) simplify data capture in high speed systems
  • Single multiplexed address input bus latches address inputs for read and write ports
  • Separate port selects for depth expansion
  • Synchronous internally self-timed writes
  • QDR® II operates with 1.5 cycle read latency when DOFF is asserted HIGH
  • Full data coherency, providing most current data
  • Core VDD = 1.8 V (±0.1 V); I/O VDDQ = 1.4 V to VDD
  • Supports both 1.5 V and 1.8 V I/O supply
  • Available in 165-ball FBGA package (13 × 15 × 1.4 mm)
  • Offered in both Pb-free and non Pb-free packages
  • Variable drive HSTL output buffers
  • JTAG 1149.1 compatible test access port
  • PLL for accurate data placement
Pricing Section
Global Stock:
0
USA:
0
On Order:
0
Factory Stock:Factory Stock:
0
Factory Lead Time:
42 Weeks
Minimum Order:
1
Multiple Of:
1
Total
$43.11
USD
Quantity
Web Price
1
$43.11
4
$39.64
10
$37.51
25
$35.48
40+
$34.49
Product Variant Information section