Manufacturer Part #
CY7C1315KV18 Series 18 Mb (512 K x 36) 1.7 - 1.9 V QDR® II SRAM - FBGA-165
|Standard Pkg:|| |
Product Variant Information section
1 per Tray
Description of Change: This notification is to inform customers that Cypress will be standardizing its Full Box Quantity to a sellable quantity in the market where it will be able to round the orders in increment of this full box quantity. It may be recalled that Cypress had implemented Manufacturing Label and Packing Configuration Standardization via Product Information Notification PIN195102 in December 2019. As part of the Cypress integration into Infineon Shipping Standard, Cypress will be adjusting Minimum Order Quantity (MOQ), Order Increment (OI) to align them with new Full Box Quantity for select parts shipped in trays and tubes.
Addendum to PIN195102 - Manufacturing Label and Packing Configuration Standardization Description of Change: The purpose of this addendum is to correct the date from January 20, 2019 to January 20, 2020, in the "3rd paragraph in the 'Description of Change' section. This notification is to inform customers that Cypress will be standardizing its manufacturing labels and tray/tube packing configuration. It may be recalled that the Cypress entity consolidation (following the merger with Spansion Corp) was announced via Product Information Notification PIN174801 in November 2017. As the next phase of the entity consolidation process, Cypress will be adapting a new manufacturing label format for all products and revising shipping configurations for select product shipped in trays and tubes.
Planned Qualification of Spansion Manufacturing Sites for Cypress ProductsDescription of Change:In concert with the recently announced merger between Cypress Semiconductor Corporation (Cypress) and Spansion Inc. (Spansion), Cypress announces plans to qualify proprietary SONOS Technology products at Spansion Fab 25 / Test 25 in Austin, Texas and BGA/TSOP-packaged products at the Spansion assembly facility in Bangkok, Thailand. These qualifications and implementations are expected to occur throughout 2015 and 2016. Once complete, the qualifications will be announced through regular PCNs.This is an advance notification and no immediate action is needed. Refer to the attached Supplier documentation for the complete schedule of the activity, PCN issue dates and shipment start dates.
|Memory Organization:||512 K x 36|
|Supply Voltage-Nom:||1.7V to 1.9V|
|Number of Words:||512 K|
|Interface Circuit Type:||Parallel|
|Operating Temp Range:||0°C to 70°C|
|Storage Temperature Range:||-65°C to +150°C|
|Moisture Sensitivity Level:||3|
|Mounting Method:||Surface Mount|
Features & Applications
The CY7C1315KV18-250BZXC is a part of CY7C1315KV18 series 1.7 - 1.9 V 18 Mbit (512 K x 36) QDR® II SRAM available in a FBGA-165 package.
This series are of 1.8 V Synchronous Pipelined SRAMs, equipped with QDR II architecture. QDR II architecture consists of two separate ports: the read port and the write port. QDR II architecture has separate data inputs and data outputs to completely eliminate the need to ‘turnaround’ the data bus that exists with common I/O devices.
- Separate independent read and write data ports
- Supports concurrent transactions
- 333-MHz clock for high bandwidth
- Four-word burst for reducing address bus frequency
- Double data rate (DDR) interfaces on both read and write ports (data transferred at 666 MHz) at 333 Hz
- Two input clocks (K and K) for precise DDR timing
- SRAM uses rising edges only
- Two Input Clocks for Output Data (C and C) to minimize Clock skew and flight time mismatches
- Echo clocks (CQ and CQ) simplify data capture in high speed systems
- Single multiplexed address input bus latches address inputs for read and write ports
- Separate port selects for depth expansion
- Synchronous internally self-timed writes
- QDR® II operates with 1.5 cycle read latency when DOFF is asserted HIGH
- Full data coherency, providing most current data
- Core VDD = 1.8 V (±0.1 V); I/O VDDQ = 1.4 V to VDD
- Supports both 1.5 V and 1.8 V I/O supply
- Available in 165-ball FBGA package (13 × 15 × 1.4 mm)
- Offered in both Pb-free and non Pb-free packages
- Variable drive HSTL output buffers
- JTAG 1149.1 compatible test access port
- PLL for accurate data placement
1 per Tray