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Manufacturer Part #

CY7C1415KV18-250BZXC

CY7C1415KV18 Series 36M (1M x 36) QDR® II SRAM Four-Word Burst - FBGA-165

Mfr. Name: Cypress
Standard Pkg:
Product Variant Information section
Date Code:
Product Specification Section
Technical Attributes
Attributes Table
Memory Density: 36Mb
Memory Organization: 1 M x 36
Supply Voltage-Nom: 1.7V to 1.9V
Access Time-Max: 0.45ns
Temperature Grade: Commercial
Speed: 250MHz
Number of Words: 1 M
Word Length: 36b
Supply Current: 640mA
Interface Circuit Type: Parallel
Operating Temp Range: 0°C to 70°C
Storage Temperature Range: -65°C to +150°C
Moisture Sensitivity Level: 3
Package Style:  FBGA-165
Mounting Method: Surface Mount
Features & Applications
The CY7C1415KV18-250BZXC is a 1.8 V synchronous pipelined SRAM, equipped with QDR II architecture. Available in a FBGA-165 package.

QDR II architecture consists of two separate ports: the read port and the write port to access the memory array. The read port has dedicated data outputs to support read operations and the write port has dedicated data inputs to support write operations.

Features:

  • Separate independent read and write data ports
  • Supports concurrent transactions
  • 333 MHz clock for high bandwidth
  • Four-word burst for reducing address bus frequency
  • Double data rate (DDR) Interfaces on both read and write ports (data transferred at 666 MHz) at 333 MHz
  • Two input clocks (K and K) for precise DDR timing
  • SRAM uses rising edges only
  • Two input clocks for output data (C and C) to minimize clock skew and flight time mismatches
  • Echo clocks (CQ and CQ) simplify data capture in high speed systems
  • Single multiplexed address input bus latches address inputs for read and write ports
  • Separate port selects for depth expansion
  • Synchronous internally self-timed writes
  • QDR® II operates with 1.5 cycle read latency when DOFF is asserted HIGH
  • Operates similar to QDR I device with 1 cycle read latency when DOFF is asserted LOW
  • Available in × 8, × 9, × 18, and × 36 configurations
  • Full data coherency, providing most current data
  • Core VDD = 1.8 V (±0.1 V); I/O VDDQ = 1.4 V to VDD
  • Supports both 1.5 V and 1.8 V I/O supply
  • Available in 165-ball FBGA package (13 × 15 × 1.4 mm)
  • Offered in both Pb-free and non Pb-free Packages
  • Variable drive HSTL output buffers
  • JTAG 1149.1 compatible test access port
  • Phase locked loop (PLL) for accurate data placement
Pricing Section
Stock:
0
Minimum Order:
136
Multiple Of:
136
On Order:
0
Factory Stock:Factory Stock:
0
Factory Lead Time:
N/A
Total
$4,678.40
USD
Quantity
Web Price
136+
$34.40
Product Variant Information section