Manufacturer Part #
dsPIC30F Series 2 kB RAM 48 kB Flash 16-Bit Digital Signal Controller - QFN-44
|Standard Pkg:|| |
Product Variant Information section
45 per Tube
Description of Change:Qualification of MMT as an additional assembly site for selected products of 0.25um, 0.18um TSMC, 70nm SMIC, Vanguard,120K,130K, 150K, 160K, 165K, 200K and 290K wafer technologies in 44L, 28 QFN-S, 20L,16L and 28L QFN packages.Pre Change:Assembled at MTAI assembly site.Post Change:Assembled at MTAI or MMT assembly site.Reason for Change:To improve on-time delivery performance by qualifying MMT as an additional assembly site Estimated First Ship Date:June 24, 2018 (date code:1826)
Revision History:January 16, 2018: Issued initial notification.April 26, 2018: Issued final notification. Attached is the qualification report. Provided estimated first ship date to be on May 26, 2018. Description of Change:Qualification of MMT as an additional site for selected products of 150K and 160K wafer technologies available in 44 QFN (8x8mm), 28L QFN-S(6x6mm), 28L QFN(6x6mm), 20L QFN (4x4mm), 16L QFN((4x4mm) and 16L QFN(3x3mm) packages. Pre Change: Assembled at MTAI assembly sitePost Change: Assembled at MTAI or MMT assembly site.Reason for Change:To improve on-time delivery performance by qualifying MMT as an additional assembly site.Estimated First Ship Date:May 26, 2018(date code: 1821)
|Program Memory Type:||Flash|
|Flash Size (Bytes):||48kB|
|No of I/O Lines:||30|
|InterfaceType / Connectivity:||CAN/I2C/SPI/UART|
|Number Of Timers:||5|
|Supply Voltage:||2.5V to 5.5V|
|Operating Temperature:||-40°C to +85°C|
|Mounting Method:||Surface Mount|
Features & Applications
The DSPIC30F4011-30I/ML is a high-performance motor control digital signal controller with an operating voltage range of 2.5 to 5.5 V and a program memory of 48 kB, available in QFN-44 package.
- High-Performance Modified RISC CPU:
- Modified Harvard architecture.
- C compiler optimized instruction set architecture.
- 84 base instructions with flexible addressing modes.
- 24-bit wide instructions, 16-bit wide data path.
- 16 x 16-bit working register array.
- Up to 30 MIPs operation:
- DC to 40 MHz external clock input.
- 4 MHz-10 MHz oscillator input with PLL active (4x, 8x, 16x).
- Peripheral and External interrupt sources.
- 8 user selectable priority levels for each interrupt.
- 4 processor exceptions and software traps.
- Primary and Alternate interrupt Vector Tables.
- DSP Engine Features:
- Modulo and Bit-Reversed Addressing modes.
- Two, 40-bit wide accumulators with optional saturation logic.
- 17-bit x 17-bit single cycle hardware fractional/ integer multiplier.
- Single cycle Multiply-Accumulate (MAC) operation.
- 40-stage Barrel Shifter.
- Dual data fetch.
45 per Tube