|Program Memory Type||ROMLess|
|No of I/O Lines||51|
|InterfaceType / Connectivity||EBI/EMI/Ethernet/IrDA/I2C/Microwire/SPI/SSI/SSP/UART/USART/USB OTG|
|Peripherals||DMA/I2S/LCD/Motor Control PWM/PWM/Watchdog|
|Number Of Timers||6|
|Supply Voltage||0.9V to 3.6V|
|Operating Temperature||-40°C to +85°C|
Features and Applications
The LPC3250FET296/01,5 is an embedded 16/32-bit ARM microcontroller designed for low power, high performance applications. It is available in 296 pin TFBGA package.
This device includes 256 kB of on-chip static RAM, a NAND flash interface, an Ethernet MAC, an LCD controller that supports STN and TFT panels, and an external bus interface that supports SDR and DDR SDRAM as well as static devices.
- ARM926EJS processor, running at CPU clock speeds up to 266 MHz
- Vector Floating Point (VFP) coprocessor.
- 32 kB instruction cache and a 32 kB data cache.
- Up to 256 kB of Internal SRAM (IRAM).
- Selectable boot-up from various external devices: NAND flash, SPI memory, USB, UART, or static memory.
- Multi-layer AHB system that provides a separate bus for each AHB master, including both an instruction and data bus for the CPU, two data busses for the DMA controller, and another bus for the USB controller, one for the LCD, and a final one for the Ethernet MAC. There are no arbitration delays in the system unless two masters attempt to access the same slave at the same time.
- External memory controller for DDR and SDR SDRAM as well as for static devices.
- Two NAND flash controllers: One for single-level NAND flash devices and the other for multi-level NAND flash devices.
- Master Interrupt Controller (MIC) and two Slave Interrupt Controllers (SIC), supporting 74 interrupt sources.
- Eight channel General Purpose DMA (GPDMA) controller on the AHB that can be used with the SD card port, the high-speed UARTs, I2S-bus interfaces, and SPI interfaces, as well as memory-to-memory transfers.
- Standard ARM test/debug interface for compatibility with existing tools.
- Emulation Trace Buffer (ETB) with 2048 ´ 24 bit RAM allows trace via JTAG.
- Stop mode saves power while allowing many peripheral functions to restart CPU activity.
- On-chip crystal oscillator.
- An on-chip PLL allows CPU operation up to the maximum CPU rate without the requirement for a high frequency crystal. Another PLL allows operation from the 32 kHz RTC clock rather than the external crystal.
- Boundary scan for simplified board testing.
- 296 pin TFBGA package with a 15 ´ 15 ´ 0.7 mm body.
- Network control