Manufacturer Part #
32bit MPU ARM Cortex A5,1.2v, BGA,-40 to 85
Description of Change: 1) Template update: Moved from Atmel to Microchip template.2) The datasheet is assigned a new document number (DS60001609) and revision letter is reset to A.3) Document number DS60001609 revision A corresponds to what would have been 11121 revision G.4) ISBN number assigned.5) Section 3. Package and Pinout: Table 3-1 SAMA5D3 Pinout for 324-ball LFBGA Package and Table 3-2 SAMA5D3 Pinout for 324-ball TFBGA Package: modified detail on Reset State for PE26. Added table note on Reset State. Added GMAC to Table 3-3 SAMA5D3 I/O Type Description.6) Section 4. Power Considerations: updated description of Table 4-1 SAMA5D3 Power Supplies. Updated Section 4.2 Power Sequence Requirements.7) Section 8. Peripherals: updated �Reserved� PIDs in Table 8-1 Peripheral Identifiers.8) Section 10. Debug and Test: updated Figure 10-1 Debug and Test Block Diagram. 9) Section 11. Standard Boot Strategies: updated nbSectorPerPage description in section NAND Flash Specific Header Detection. 10) Section 14. Bus Matrix (MATRIX): updated Matrix slaves.11) Section 22. Real-time Clock (RTC): deleted all references to Register Write Protection. 12) Section 25. Clock Generator: added CAL field detail in Section 25.5.2 12 MHz RC Oscillator Clock Frequency Adjustment.13) Section 29. Multi-port DDR-SDRAM Controller (MPDDRC): modified row range in Table 29-8 Interleaved Mapping DDR-SDRAM Configuration Mapping: 8K Rows, 512/1024/2048 Columns, 4 banks. 14) Section 33. Image Sensor Interface (ISI): added important note to Section 33.4.2 Power Management.15) Section 36. Gigabit Ethernet MAC (GMAC): updated Section 36.9.10 GMAC Interrupt Status Register, Section 36.9.11 GMAC Interrupt Enable Register, Section 36.9.12 GMAC Interrupt Disable Register, Section 36.9.13 GMAC Interrupt Mask Register with TSUTIMCOMP bit (index 29).16) Section 37. Ethernet 10/100 MAC (EMAC): updated Section 37.4.14 Physical Interface with support for RMII only. 17) Section 39. Serial Peripheral Interface (SPI): deleted REQCLR bit in Section 39.8.1 SPI Control Register. 18)Section 40. Two-wire Interface (TWI): updated Figure 40-25 Master Performs a General Call. Updated bit descriptions CHDIV, CLDIV in Section 40.8.5 TWI Clock Waveform Generator Register.19) Section 54. Electrical Characteristics: Table 54-2 DC Characteristics: added RPULL for GMAC pads. Section 54.16 SSC Timings: updated Figure 54-23 SSC Transmitter, TK and TF in Input; updated Table 54-60 SSC Timings with 3.3V Peripheral Supply and Table 54-61 SSC Timings with 1.8V Peripheral Supply. Added Section 54.20 USART in Asynchronous Modes. Table 54-73 Two-wire Serial Bus Requirements: updated formulae in Note (2).20) Section 55. Mechanical Characteristics: added reference to Microchip Packaging Specification. 21) Section 56. Schematic Checklist: updated Description for VDDIOM in Table 56-1 Power Supply Connections.22) Section 59. Errata: Added errata: Section 59.6.2 DMAC: Not possible to transfer data with DMA to the SHA when SHA384 or SHA512 algorithm is selected Section 59.9.3 GMAC: Bad association of timestamps and PTP packets Section 59.11.1 USART: USART Framing error not detected if last data bit is 1.Reason for Change: To Improve ProductivityDate Document Changes Effective: 6 Feb 2020.NOTE: Please be advised that this is a change to the document only the product has not been changed.