Manufacturer Part #
MACHX02 Series 640 LUT 79 I/O 2.5 / 3.3 V Non-volatile FPGA - TQFP-100
|Mfr. Name:||Lattice Semiconductor|
|Standard Pkg:|| |
Product Variant Information section
90 per Tray
Lattice Semiconductor is providing this notification of a change to the Power Calculator tool that is used in Lattice Diamond 3.12 software (Release Date: December 8, 2020). This PCN covers one change to the calculation of the MCLK (oscillator) entry to the MISC tab of Power Calculator. This change affects the software only, and has no impact to silicon or hardware. Change Description:This change is a modification to how Power Calculator computes power for the MCLK when it is used. The power consumed by the used MCLK in Power Calculator will increase. The default setting of MCLK is to be used. Thus this change will affect the Power Calculator in instances when it is brought up in default settings (blank pattern), or in any Estimation or Calculation for non-default settings (user pattern) where MCLK is used. When the MCLK is unused, there will be no effect on Power Calculator. The magnitude of the power increase will vary depending on the voltage. For parts with a core VCC of 2.5v or 3.3v, the increase will be 15.5mW � 1mW for XO2, XO3L, and XO3LF. That increase will be 43.5mW � 1mW for XO3D, and 41.0mW � 1mW for Platform Manager 2. For parts with a core VCC of 1.2v, the increase will be 5.3mW � 1mW.
Notification of Removal of Device Backside Mark on all Lattice QFP Products Lattice is providing this notification of our intent to remove the backside marking for Lattice Quad Flat Pack (QFP) products. The backside marking removal will be a gradual transition until existing inventories have been exhausted. The manufacturing process will be changed on or after December 28, 2020 and the realization of the removal by the customer will be a gradual transition over time, depending on the individual products' inventory levels. Backside marking consists of the Date Code (YYWW) and Assembly Lot number. These are both being marked in package assembly. Currently, backside marking is utilized only for internal traceability. The device and assembly lot will maintain traceability with the Inspection Lot (topside lot number). The change is aimed to standardize with current industry practices.
|No of I/O Lines:||79|
|No of Logic Elements:||640|
|Supply Voltage:||2.375V to 3.465V|
|Mounting Method:||Surface Mount|
90 per Tray