text.skipToContent text.skipToNavigation





By Nexperia


Our homes are filled with electronics products, such as printers, televisions and set-top boxes, which have a standby or partial power-down mode. And despite the overall trend towards lower operating voltages, numerous home entertainment and computing peripherals continue to run from a 5V supply rail.

These 5V systems have just as much need for power-saving circuit features as devices operating at lower voltages such as 2.5V or 3.3V. This is why Nexperia has extended its power-saving logic technology to be compatible with 5V nodes.

Partial Power-Down Logic Technology

So-called IOFF circuitry is a logic technology feature which supports partial power-down, and is used in modular standby applications. IOFF circuitry has long been available on Nexperia’s CMOS low-power AUP, AVC, AXP and LVC logic device families.

Now, following the introduction of the LV-A(T) family, Nexperia’s standard CMOS logic portfolio is expanded to include partial-power down types which address the 5V node, in addition to 2.5V and 3.3V nodes for which LV-A is also fully specified.

How Partial Power-Down Works

Partial power-down involves shutting down unused parts of a circuit. It is mainly used to keep devices in standby mode. Logic technologies which support IOFF have no leakage path to the supply rails when the supply voltage is zero. The IOFF protection circuitry ensures that an excessive current may not be drawn from the input and output, preventing damage to subsystems, as shown in Figure 1.

Fig. 1: Disabling the flow of power using the IOFF feature

Nexperia’s LV-A(T) family of devices are notable for their low leakage when powered down. The LV-A(T) technology is rated for 0.1μA typical static current, and offers low propagation delay, as shown in the table below.

  Supply Voltage (VCC) Output Drive (VO) Prop Delay (tPD) Temperature Range (Tamb) Static Current (ICC)
LV-A 2.0 – 5.5V ±16mA 4.9ns @ 2.5V
3.7ns @ 3.3V
2.9ns @ 5.0V
-40°C to 125°C 0.1μA (typ.)
LV-AT 4.5 – 5.5V ±16mA 2.9ns @ 5.0V -40°C to 125°C 0.1μA (typ.)


LV-A(T) also features low noise, specified as Vol(p) <0.8V. As shown in Figure 2, Vol(p), Vol(v) is when one output is driven Low while other outputs simultaneously switch from High to Low. Voh(v), Voh(p) is when one output is driven High while other outputs simultaneously switch from Low to High.

Fig. 2: LV-A noise characteristics at VCC = 5V

LV-A types of logic devices feature CMOS input levels, while LV-A(T) types include lowinput thresholds for TTL interfacing. Both LV-A and LV-A(T) types feature Schmitt trigger action, which produces a small input-switching hysteresis of around 100mV: this improves noise immunity, as shown in Figures 3 and 4. True Schmitt trigger inputs are available in the 74LV14A and 74LV17A series of devices, as shown in Figure 5.

Fig. 3: LV-A CMOS input with Schmitt action at 5V

Fig. 4: LV-A(T) TTL inputs with Schmitt action at 5V

Fig. 5: LV-A Schmitt trigger inputs at 5V

LV-A products operate with defined low input levels of ≤0.3xVCC and high input levels of ≥0.7xVCC at a supply-voltage range of 2.0V to 5.5V.

For LV-A(T) products, the low input level is ≤0.8V and the high input level is ≥2.0V at a supply-voltage range of 4.5V to 5.5V.

LV-A(T) Additional Features: Over-Voltage Tolerant Inputs and Open-Drain Outputs

With over-voltage tolerant inputs, the maximum voltage applied to an input may exceed the supply voltage. For LV-A(T) devices, 5.5V may be applied to the inputs irrespective of the supply voltage. Thanks to this feature, LV-A solutions are suitable for High-to-Low level translation. For example, when supplied at 3.3V, 5.0V may be applied to the input to achieve 5.0V to 3.3V voltage translation. Because of their low-threshold inputs, LV-A(T) solutions are suitable for Low-to-High level translation. For example, when supplied at 5.0V, 3.3V may be applied to the input to achieve 3.3V to 5.0V voltage translation.

Options with open-drain outputs include outputs with only an NMOS transistor to ground. To achieve a logical High on the output when the product is in the high-impedance state, or 3-state, a pull-up resistor can be used to reach the desired output-voltage level. The pull-up resistor can be used with a pull-up voltage higher or lower than the supply voltage.

Independent of the supply voltage, open-drain LV-A(T) solutions can be used with a pull-up voltage of 5.5V or lower, which allows for voltage translation.

Nexperia’s LV-A(T) and LV-A Portfolios

Nexperia’s LV-A(T) portfolio is comprised of logic buffers, inverters and transceivers. The LV-A portfolio also includes AND, OR, NAND and NOR gates.

A total of 18 types are available in this family, all in industry-standard TSSOP packages, as shown.


FTM NA SideNav SubscribeTile EN
FTM NA Issue7-2019 SideNav Download