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Advanced Timing for Next Gen Networking

SERDES, transceivers and RF converters benefit from low phase noise and low jitter clocking to meet the growing market demand for higher data rates and bandwidth. CPUs, FPGAs, RF chipsets and ASSPs driving next generation OTN, 100/400G Ethernet, FibreChannel, RF and PCI Express physical layer interfaces need clock jitter below 100fsec to achieve acceptable design margin. Applications such as base stations (BTS) and high accuracy GPS equipment requiring long periods of holdover utilize ultra-precise 100ppb to 0.1ppb clock references to generate a local time base.