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23K256-I/SN
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100 par Tube
SOIC-8
Surface Mount
Informations de livraison:
Code HTS:
ECCN:
Informations PCN:
Description of Change: Qualification of palladium coated copper with gold flash (CuPdAu) as an additional bond wire material and QMI519 as an additional die attach material for 23A256-I/SN, 23A256T-I/SN, 23A640-I/SN, 23A640T-I/SN, 23K256-E/SN, 23K256-I/SN, 23K256T-E/SN, 23K256T-I/SN, 23K640-E/SN, 23K640-I/SN, 23K640T-E/SN and 23K640T-I/SN catalog part numbers (CPN) available in 8L SOIC (3.90mm) package at MTAI assembly site.Pre and Post Summary Changes: See attched SPCN document for more detailsReason for Change: To improve manufacturability by qualifying palladium coated copper with gold flash (CuPdAu) as an additional wire material and QMI519 as a new die attach material.Change Implementation Status: In ProgressEstimated Qualification Completion Date: September 2026
Description of Change:Implementation of Inner Box, Reel and MSL Bag Label changes for virtually ALL Microchip products.Reason for Change:To improve productivity by implementing inner box, reel and MSL bag label changes.
Microchip has released a new Datasheet for the 23A256/23K256 - 256-Kbit SPI Bus Low-Power Serial SRAM of devices. If you are using one of these devices please read the document located at 23A256/23K256 - 256-Kbit SPI Bus Low-Power Serial SRAM.Notification Status: FinalDescription of Change: Updated section 2.1: ?Principles of Operation?.Impacts to Data Sheet: See above detailsReason for Change: To Improve ProductivityChange Implementation Status: CompleteDate Document Changes Effective: 13 Oct 2023NOTE: Please be advised that this is a change to the document only the product has not been changed.Markings to Distinguish Revised from Unrevised Devices: N/A
Statut du produit:
The 23X256 are 256 Kbit Serial SRAM devices. The memory is accessed via a simple Serial Peripheral Interface (SPI) compatible serial bus. The bus signals required are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled through a Chip Select (CS) input.
Communication to the device can be paused via the hold pin (HOLD). While the device is paused, transitions on its inputs will be ignored, with the exception of Chip Select, allowing the host to service higher priority interrupts. The 23X256 is available in standard packages including 8-lead PDIP and SOIC, and advanced packaging including 8-lead TSSOP.
Features:
Learn more about the 23K256 family of Memory Device
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