Nexperia | 74HCT573PW,118

The 74HCT573PW is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL).

The 74HC573; 74HCT573 has octal D-type transparent latches featuring separate D-type inputs for each latch and 3-state true outputs for bus oriented applications. A latch enable (LE) input and an output enable OEinput are common to all latches. When LE is HIGH, data at the Dn inputs enter the latches. In this condition the latches are transparent, i.e. a latch output will change state each time its corresponding D input changes.

Features:

• Inputs and outputs on opposite sides of package allowing easy interface with microprocessors
• Useful as input or output port for microprocessors and microcomputers
• 3-state non-inverting outputs for bus oriented applications
• Common 3-state output enable input
• Functionally identical to 74HC563; 74HCT563 and 74HC373; 74HCT373
• Complies with JEDEC standard no. 7A
• ESD protection:
  • HBM EIA/JESD22-A114-C exceeds 2000 V
  • MM EIA/JESD22-A115-A exceeds 200 V
• Specified from -40 Cel to +85 Cel from -40 Cel +125 Cel