The high-speed PCIe interface standard is used to connect endpoints in a computing platform, such as video cards, storage devices, network adaptors, and AI accelerators, to a microprocessor. Switchtec PCIe products are widely used in data center servers. Now Microchip has introduced the smaller PCI100x packet switches for use in edge compute and edge AI systems to connect systems-on-chip (SoCs) and neural networking accelerators. The PCI100x series is also suitable for the fan-out of port- and lane-limited PCIe connections.
The PCI100x packet switches conform to the specifications of the PCIe Base Specification 4.0, and support up to 16 lanes with non-transparent bridge (NTB) options. They provide embedded low-power states: advanced power-saving features include idling of empty ports, and clock removal during L1 states.
End-to-end data integrity protection and low-latency performance are consistent with other Switchtec products. Typical packet latency is 120 ns for port-to-port transit.
Comprehensive diagnostics and debugging capabilities are available through the Microchip ChipLink tool suite. Diagnostic capabilities include PCIe analyzer and configurable stack error counters, eye opening margining, and firmware logging.
The PCI100x devices are supplied in a 353-ball chip-scale package with a footprint of 16 mm x 16 mm.
Part Number | Ports | UFP Configuration | DFP Configuration | NTB Provision | Automotive Temperature Option |
PCI1001 | 4 | 1×4 lane port | 3×4 lane ports | 0 | No |
PCI003 | 6 | 2×4 lane ports and 2×2 lane ports | 2x2lLane ports | 4 | Yes |
PCI004 | 4 | 4×4 lane ports | 0 | 4 | Yes |
PCI005 | 7 | 1×4 lane port | 6×2 lane ports | 0 | No |
