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Référence fabricant
AVR128DB48-I/PT
128KB, TQFP48, 85C, 24MHz, 12b ADC, Comp, Opamp, MVIO, ZCD, DAC, UART, SPI, TWI
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| Nom du fabricant: | Microchip | ||||||||||
| Emballage standard: | Product Variant Information section Emballages disponiblesQté d'emballage(s) :250 par Tray Style d'emballage :TQFP-48 Méthode de montage :Surface Mount | ||||||||||
| Code de date: | |||||||||||
Microchip AVR128DB48-I/PT - Spécifications du produit
Informations de livraison:
ECCN:
Informations PCN:
Description of Change: Qualification of QMI519 as a new die attach material for selected PIC18F56K42, PIC18F55K42, PIC18F57Q43, PIC18F56Q83, PIC18F56Q84, AVR32DA48, PIC18F57Q83, PIC18F57Q84, PIC18F56Q43, PIC18F54Q71, PIC18F55Q71, PIC18F56Q71, AVR128DA48, PIC16F15385, PIC16F15386, AVR64DB48, AVR32DB48, AVR128DB48, AVR64DA48, PIC16F19186, PIC16F19185, PIC18F55Q43, PIC18F55Q24, PIC18F56Q24 and PIC18F57K42 device families available in 48L TQFP (7x7x1mm) package at MTAI assembly site.Reason for Change: To improve manufacturability by qualifying QMI519 as a new die attach material.Estimated First Ship Date: 23 June 2025 (date code: 2526)
Description of Change:• Document:o General editorial updateso Back Matter and PDF front cover updates• Added Erratum for silicon Rev. A4, Rev. A5 and Rev. B0:o ADC: ADC MUX Selection and Accumulation Number has Delayed Update When Initialization Delay is Usedo TCB: TCB4 Waveform Output Alternative 1 Non-Functional• Added Data Sheet Clarifications:o Device: FUSE - Configuration and User Fuseso CLKCTRL - Clock Controller: Interruptso RSTCTRL - Reset Controller: Domains Affected By Reseto SLPCTRL - Sleep Controller: Sleep Modeso SPI - Serial Peripheral Interface: Client Modeo SPI - Serial Peripheral Interface: Buffer Modeo UPDI - Unified Program and Debug Interface: UPDI - Reset Controllero Electrical Characteristics: USARTo Electrical Characteristics: ACo Electrical Characteristics: ADCo Electrical Characteristics: DACo Characteristics Graphs: BODReason for Change: To improve productivity.Date Document Changes Effective: 25 Apr 2025
Microchip has released a new Document for the AVR128DB28/32/48/64 Silicon Errata and Data Sheet Clarification of devices.Notification Status: FinalDescription of Change:• Document: General editorial updates• Added Errata for silicon Rev. B0:– Device: 2.2.4. Write Operation Lost if Consecutive Writes to Specific Address Spaces– NVMCTRL: 2.7.2. NVM_EEPROM_ERASE Command does Not Respect Write Protect– PORT: 2.9.1. PD0 Input Buffer is Floating– TCD: 2.14.3. Halting TCD and Waiting for SW Restart Does Not Work if Compare Value A is 0 orDual Slope Mode is Used– TWI: 2.15.2. Flush Non-Functional– USART: 2.16.3. Receiver Non-Functional after Detection of Inconsistent Synchronization Field• Added Data Sheet Clarifications:– SPI: 3.1.1. SPI - Serial Peripheral Interface– SPI: 3.1.2. SPI - Serial Peripheral Interface– Electrical Characteristics: 3.2.1. I/O Pins– Electrical Characteristics: 3.2.2. SPIImpacts to Data Sheet: NoneChange Implementation Status: CompleteDate Document Changes Effective: 01 May 2024NOTE: Please be advised that this is a change to the document only the product has not been changed.Markings to Distinguish Revised from Unrevised Devices: N/A
Microchip has released a new Errata for the Silicon Errata and Data Sheet Clarification of devices. If you are using one of these devices please read the document located at Silicon Errata and Data Sheet Clarification.Notification Status: FinalDescription of Change: Revision includes:? Document: General editorial updates? Added Errata: ? SPI: 2.11.1. Alternative 2 Pin Position is Non-Functional for SPI1 with 48-Pin Devices ? USART: 2.16.3. Receiver Non-Functional after Detection of Inconsistent Synchronization Field? Removed all data sheet clarifications as they are fixed in the current device data sheet (www.microchip.com/DS40002247)Impacts to Data Sheet: NoneReason for Change: To Improve ProductivityChange Implementation Status: CompleteDate Document Changes Effective: 03 January 2023NOTE: Please be advised that this is a change to the document only the product has not been changed.Markings to Distinguish Revised from Unrevised Devices::N/A
Microchip has released a new Product Documents for the AVR64DB28/32/48/64 Silicon Errata and Data Sheet Clarifications of devices. Notification Status: FinalDescription of Change:Document: General editorial updates.Added errata:? DAC: 2.4.1. DAC Output Buffer Lifetime Drift? NVMCTRL: 2.5.1. Flash Multi-Page Erase Can Erase Write Protected Section? TCD: 2.8.3. Halting TCD and Waiting for SW Restart Does Not Work if Compare Value A is 0 or Dual Slope Mode is Used? TWI: 2.9.1. Flush Non-FunctionalAdded data sheet clarifications:? Device: 3.1.1. Features3.1.2. FUSE - Configuration and User Fuses - SYSCFG0? AC: 3.2.1. Analog Comparator Interrupt Control? DAC: 3.3.1. DAC Output? Electrical Characteristics: 3.4.1. Electrical Characteristics - Memory Programming Specifications Impacts to Data Sheet: NoneReason for Change: To Improve ProductivityChange Implementation Status: CompleteDate Document Changes Effective: 25 March 2022
Microchip has released a new Product Documents for the AVR128DB28/32/48/64 Silicon Errata and Data Sheet Clarifications of devices.Notification Status: FinalDescription of Change:Document: General editorial updates.Added errata:- Device: 2.2.3. CRC Check During Reset Initialization Is not Functional- CLKCTRL: 2.5.3. PLL Status not Working as Expected- DAC: 2.6.1. DAC Output Buffer Lifetime Drift- NVMCTRL: 2.7.1. Flash Multi-Page Erase Can Erase Write Protected Section- TCA: 2.11.1. Restart Will Reset Counter Direction in NORMAL and FRQ Mode- TCD: 2.13.3. Halting TCD and Waiting for SW Restart Does Not Work if Compare Value A is 0 or Dual Slope Mode is Used- TWI: 2.14.2. Flush Non-FunctionalUpdated Errata:- 2.15.2. Start-of-Frame Detection Can Unintentionally Be Triggered in Active ModeAdded data sheet clarifications:- 3.1.1. Features- 3.1.2. FUSE - Configuration and User Fuses - SYSCFG0- 3.1.3. Peripherals and Architecture - REVID- 3.2.1. Voltage Regulator Control (VREGCTRL)- 3.3.1. Single-Shot Mode- 3.4.1. Analog Comparator Interrupt Control- 3.5.1. DAC Output- 3.6.1. Electrical Characteristics - Memory Programming SpecificationsImpacts to Data Sheet: NoneReason for Change: To Improve ProductivityChange Implementation Status: CompleteDate Document Changes Effective: 25 March 2022
Statut du produit:
Microchip AVR128DB48-I/PT - Caractéristiques techniques
| Family Name: | AVR128 |
| Core Processor: | AVR |
| Program Memory Type: | Flash |
| Flash Size (Bytes): | 128kB |
| RAM Size: | 16kB |
| Speed: | 24MHz |
| No of I/O Lines: | 41 |
| InterfaceType / Connectivity: | I2C/SPI/UART/USART |
| Peripherals: | Brown-out Detect/POR/PWM/Reset/Watchdog |
| Supply Voltage: | 1.8V to 5.5V |
| Operating Temperature: | -40°C to +85°C |
| On-Chip ADC: | 18-chx12-bit |
| On-Chip DAC: | 1-chx10-bit |
| Style d'emballage : | TQFP-48 |
| Méthode de montage : | Surface Mount |
Emballages disponibles
Qté d'emballage(s) :
250 par Tray
Style d'emballage :
TQFP-48
Méthode de montage :
Surface Mount