FTM / Motor Control / Lattice Semiconductor — sensAI™ 3.0 Solutions Stack
The latest version of Lattice Semiconductor’s complete solutions stack for on-device Artificial Intelligence (AI) processing at the edge, Lattice sensAI™ 3.0, has added support for the CrossLink-NX™ family of FPGAs for low-power smart vision applications. The Lattice AI stack also now includes Convolutional Neural Network (CNN) accelerator IP embedded in the CrossLink-NX FPGA which simplifies implementation of common CNN networks, and which takes advantage of the parallel-processing capabilities of FPGAs.
By enhancing the sensAI stack, Lattice has widened the range of power and performance options available to OEMs to implement AI at the edge. For applications such as smart vision and object recognition, which require high edge AI performance, CrossLink-NX FPGAs running sensAI software provide twice the performance at half the power when compared to prior releases of the stack.
Most edge devices are battery-powered or otherwise sensitive to power consumption. The sensAI 3.0 stack enables developers to specify the processing capabilities needed for AI applications, while keeping power consumption as low as possible. In addition, CrossLink-NX FPGAs are fabricated in a 28nm process which offers a 75% reduction in power consumption compared to that of competing bulk CMOS FPGAs in the same class.
The sensAI software stack is backed by new, ready-to-use demonstrations and reference designs for popular AI applications. These include a CrossLink-NX-based object-counting demonstration using the VGG neural networking algorithm. Running on a CrossLink-NX FPGA, it scans at a rate of 10 frames/s while consuming only 200mW.
Other new and updated features of the sensAI solutions stack include:
Board part number: LIFCL-40-EVN
The CrossLink-NX evaluation board includes a USB-B connection for device programming and an I2C utility, 128Mbits of SPI boot Flash, eight input DIP switches, four push buttons, three status LEDs, 14 LEDs for demonstration purposes, and multiple reference clock sources.
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