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Manufacturer Part #
MPFS025T-FCSG325I
PolarFire SoC FPGA, RISC-V CPU, 23KLEs 325 TFBGA 11x11x1.35mm TRAY
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| Mfr. Name: | Microchip | ||||||||||
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Product Variant Information section
Available PackagingPackage Qty:1 per Tray |
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| Date Code: | 2536 | ||||||||||
Microchip MPFS025T-FCSG325I - Product Specification
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PCN Information:
Description of Change:Microchip has released a new Document for the PolarFire? SoC FPGA Production Devices Errata of devices. ? SD compliance tests are completed.? Added row to Table 1-1. Summary of PolarFire? SoC FPGA Errata for ?External VERIFY_DIGEST with POR Digest Check for Fabric Components.?? Deprecated Feature: Use of External VERIFY_DIGEST with POR Digest Check for Fabric Components.Reason for Change: To improve productivity. Date Document Changes Effective: 19 Sep 2025
Description of Change:Microchip has released a new Datasheet for the PolarFire? SoC Datasheet of devices.? Added reference to PolarFire Core SoC products (MPFSxxxTC) in Silicon and Libero Tool Status, Transceiver Switching Characteristics, Transceiver Protocol Characteristics, FPGA Programming Time, FPGA Bitstream Sizes, Digest Time, Verify Time, and Authentication Time. ? Changed status to Production - all temperature grades for all products in Table 2-1. ? Updated prodution status and Libero release info for MPFS460T in Table 2-2. ? Corrected the part numbers in military devices in Table 2-3. ? In Table 2-4, updated Libero version and status to Production for all devices; removed MPFS460T; added Core devices. ? Updated note 7 under Table 3-2 for XCVR calibration time. ? Added clarifying note 10 under Recommended Operating Conditions. ? Removed reference to PolarFire I/O Timing Spreadsheet in User I/O Switching Characteristics. ? Corrected note under Transceiver Performance from Untill specified to Unless specified. ? Updated note under I/O Fast Recalibration Time (TRECALIB). ? SLVS18, SUBLVDS18 and SLVS25/33 Maximum input buffer speeds have been updated in Input Buffer Speed. ? Updated Table 4-139. ? Added section SLVS-EC.Reason for Change: To improve productivity. Date Document Changes Effective: 19 May 2025
PCN Status:Final NotificationDescription of Change:Release of updated software version of Synplify Pro Microchip Edition v2023.09M-1 & Synplify Pro Standalone v2023.09-1 for various FPGA devices.Reason for Change:Synplify Pro standalone all-vendor versions 2023.03 and 2023.09, as well as Microchip Edition version 2023.09M could incorrectly extract the enable signal logic during RTL synthesis when the signal path contains a set of multiplexors connected in series around a register, and the MUXs are driven by bus ports. This is described in the attached Customer Notice.
Description of Change:Released of updated Libero SoC v2022.3 for selected products in the PolarFire FPGA device family, including MPFxxx and RTPF device families as described in the attached customer notice details.Reason for Change:Release updated Libero SoC v2022.3 to prevent usage of device programming bitstreams that could result in false Power-On Reset digest check failures and tamper flag assertion, for scenarios where the user has enabled POR digest check settings for device components not included in the programming bitstream.
Description of Change:Release of updated Synplify Pro ME version S-2021.09M-SP2 FPGA synthesis software bundled with Libero SoC v2022.3Reason for Change:Release updated Synplify Pro ME version S-2021.09M-SP2 FPGA synthesis software bundled with Libero SoC v2022.3 to prevent incorrect Verilog mapping of RTL using increment/decrement operations (++ / --) while indexing into an array on the right-hand side (RHS) of an assignment statement, as described in the attached Customer Notice.
Description of Change:Release of updated Synplify Pro ME version S-2021.09M-SP2 synthesis software bundled with Libero SoC v2022.3 as described in the attached customer notification details.Reason for Change:Release updated Synplify Pro ME version S-2021.09M-SP2 synthesis software bundled with Libero SoC v2022.3 to prevent incorrect VHDL expression evaluation during compilation, when performing subtraction with a real constant number operand, and an additional division/multiplication operation that uses a variable. This is to fix a VHDL compiler issue that occurs in specific VHDL expressions.
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Available Packaging
Package Qty:
1 per Tray