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SY89825UHY
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160 par Tray
TQFP-64
Surface Mount
Informations de livraison:
Le pays d’origine (COO) est attribué au moment de l’expédition et ne peut pas être sélectionné lors du processus de commande. Tous les documents indiqueront le COO au moment de l’expédition.
Code HTS:
ECCN:
Informations PCN:
***FPCN106550 UPDATE***Revision History:July 19, 2024: Issued initial notification.January 23, 2025: Issued final notification. Attached the Qualification Report. Provided estimated first ship date to be on February 15, 2025.Description of Change:Qualification of MTAI as an additional assembly site for selected SY89467U, SY89825U, SY89221U, SY89826L, SY89828L, SY89824L, SY89468U and SY89218U device families available in 64L TQFP (10x10x1.0mm) package.Reason for Change:To improve on-time delivery performance by qualifying MTAI as additional assembly site.
Description of Change:Qualification of MTAI as an additional assembly site for selected SY89467U, SY89825U, SY89221U, SY89826L, SY89828L, SY89824L, SY89468U and SY89218U device families available in 64L TQFP (10x10x1.0mm) package.Reason for Change:To improve on-time delivery performance by qualifying MTAI as additional assembly site.
**Update to previous FPCN 98050******Revise affected parts list to remove SY89829UHY, SY89829UHY-TR and SY55856UHG catalog part number since these parts were EOL?ed****Description of Change:Qualification of UNIG as a new final test site for various products available in Tube and Tape & Reel packing media.Reason for Change:To improve manufacturability and on-time delivery performance by qualifying UNIG as a new final test site.
Description of Change:Qualification of UNIG as a new final test site for various products available in Tube and Tape & Reel packing media.Reason for Change:To improve manufacturability and on-time delivery performance by qualifying UNIG as a new final test site.
Statut du produit:
The SY89825UHY is a High Performance Bus Clock Driver with 22 differential LVPECL output pairs. It is available in TQFP-64 package.
This part is designed for use in low voltage (2.5 V, 3.3 V) applications which require a large number of outputs to drive precisely aligned, ultra low skew signals to their destination. The input is multiplexed from either LVDS or LVPECL by the CLK_SEL pin. The SY89825U features low pin-to-pin skew (35ps max.) —performance previously unachievable in a standard product having such a high number of outputs. The SY89825U is available in a single space saving package which provides a lower overall cost solution.
Features:
Applications:
View the available SY8982x series of Clock Drivers
Stock conservé dans l'entrepôt du fabricant. Sous réserve de disponibilité et de temps de transit.