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Référence fabricant
A3P060-1VQG100
ProASIC3 Series 60000 System Gate 71 I/O 1.575V Surface Mount FPGA -VQFP-100
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| Nom du fabricant: | Microchip | ||||||||||
| Emballage standard: | Product Variant Information section Emballages disponiblesQté d'emballage(s) :180 par Tray | ||||||||||
| Code de date: | |||||||||||
Microchip A3P060-1VQG100 - Spécifications du produit
Informations de livraison:
ECCN:
Informations PCN:
PCN Status:Final NotificationDescription of Change:Release of updated software version of Synplify Pro Microchip Edition v2023.09M-1 & Synplify Pro Standalone v2023.09-1 for various FPGA devices.Reason for Change:Synplify Pro standalone all-vendor versions 2023.03 and 2023.09, as well as Microchip Edition version 2023.09M could incorrectly extract the enable signal logic during RTL synthesis when the signal path contains a set of multiplexors connected in series around a register, and the MUXs are driven by bus ports. This is described in the attached Customer Notice.
Microchip has released a new Datasheet for the ProASIC?3 Flash Family FPGAs with Optional Soft ARM Support of devices.Notification Status: FinalDescription of Change: In the previous version of the document, there was an error in the migration process to the Microchip template where information related to QN132 devices was not removed. This mistake has been corrected in the current revision. ? Corrected misaligned images?Figure 1-1, Figure 1-2, Figure 1-3, and Figure 2-2. ? Updated Figure 2-39 as per Revision B of the document.Impacts to Data Sheet: See above details.Reason for Change: To Improve ProductivityChange Implementation Status: CompleteDate Document Changes Effective: 18 May 2023
Description of Change:Release of updated Synplify Pro ME version S-2021.09M-SP2 FPGA synthesis software bundled with Libero SoC v2022.3Reason for Change:Release updated Synplify Pro ME version S-2021.09M-SP2 FPGA synthesis software bundled with Libero SoC v2022.3 to prevent incorrect Verilog mapping of RTL using increment/decrement operations (++ / --) while indexing into an array on the right-hand side (RHS) of an assignment statement, as described in the attached Customer Notice.
Description of Change:Release of updated Synplify Pro ME version S-2021.09M-SP2 synthesis software bundled with Libero SoC v2022.3 as described in the attached customer notification details.Reason for Change:Release updated Synplify Pro ME version S-2021.09M-SP2 synthesis software bundled with Libero SoC v2022.3 to prevent incorrect VHDL expression evaluation during compilation, when performing subtraction with a real constant number operand, and an additional division/multiplication operation that uses a variable. This is to fix a VHDL compiler issue that occurs in specific VHDL expressions.
Statut du produit:
Emballages disponibles
Qté d'emballage(s) :
180 par Tray