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25AA1024-I/SM
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90 par Tube
SOIJ-8
Surface Mount
Informations de livraison:
Code HTS:
ECCN:
Informations PCN:
Description of Change:Qualification of U08D as an additional fabrication site using 66.91K process technology for selected products of AT25M01, 25LC1024 and 25AA1024 device families available in 8L SOIC (.150in) , SOIJ (.208in), PDIP (.300in) and DFN-S (6x5x0.9mm) packages.Reason for Change:To improve manufacturability and on-time delivery performance by qualifying U08D as an additional fabrication site using 66.91K process technology.
Product Category: MemoryDescription of Change: Qualification of palladium coated copper with gold flash (CuPdAu) as a new bond wire material for selected 24AA1025, 24AA1026, 24AA128, 24AA256, 24AA32A, 24AA512, 24AA515, 24AA64, 24CS128, 24CS256, 24CS32, 24CS512, 24CS64, 24CSM01, 24CW1280, 24CW160, 24CW320, 24CW640, 24FC1025, 24FC1026, 24FC128, 24FC256, 24FC512, 24FC515, 24FC64, 24LC1025, 24LC1026, 24LC128, 24LC256, 24LC32A, 24LC512, 24LC515, 24LC64, 25AA1024, 25LC1024, AT24C512C, AT24CM01 and AT25M01 device families available in 8L SOIC (.150in) and 8L SOIJ (.208in) packages at MTAI assembly site.Reason for Change: To improve manufacturability by qualifying palladium coated copper with gold flash (CuPdAu) as a new wire material at MTAI assembly site.Estimated First Ship Date: 15 April 2026 (date code: 2616)
Description of Change:Implementation of Inner Box, Reel and MSL Bag Label changes for virtually ALL Microchip products.Reason for Change:To improve productivity by implementing inner box, reel and MSL bag label changes.
Description of Change: Qualification of 66.9k wafer technology with QMI519 as a new die attach material and Au as a new wire material for selected 25AA1024, 25LC1024 and AT25M01 device families available in 8L SOIJ (.208in) package.Reason for Change: To improve manufacturability by qualifying 66.9k wafer technology with QMI519 as a new die attach material and Au as a new wire material.
Statut du produit:
The 25AA1024 series of 1024 Kbit serial EEPROM memory with byte-level and page level. It also features Page, Sector and Chip erase functions typically associated with Flash-based products. These functions are not required for byte or page write operations. The memory is accessed via a simple Serial Peripheral Interface (SPI) compatible serial bus. The bus signals required are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled by a Chip Select (CS) input.
Communication to the device can be paused via the hold pin (HOLD). While the device is paused, transitions on its inputs will be ignored, with the exception of Chip Select, allowing the host to service higher priority interrupts. The 25AA1024 is available in standard packages including 8-lead PDIP and SOIJ, and advanced 8-lead DFN package. All devices are Pb-free.
Features:
Learn more about the 25AA1024 family of EEPROM
Sur commande
Stock conservé dans l'entrepôt du fabricant. Sous réserve de disponibilité et de temps de transit.