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EX256-TQG100
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90 par Tray
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Le pays d’origine (COO) est attribué au moment de l’expédition et ne peut pas être sélectionné lors du processus de commande. Tous les documents indiqueront le COO au moment de l’expédition.
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ECCN:
Informations PCN:
*** Update for PCN 109274 ***Description of Change: Qualification of Lead-Lock Tape for selected A54SX08A, EX256, and EX128 device families available in 100L LQFP (14x14x1.4mm) package.Reason for Change: To improve manufacturability by qualifying lead-lock tape.Estimated First Ship Date: 30 June 2025 (date code: 2527)Revision History: November 15, 2024: Issued initial notification.June 12, 2025: Issued final notification. Attached the Qualification Report. Revised the affected parts list to add EX256-TQG100PJ31 catalog part number (CPN) and removed A54SX08A-TQG100-B1, A54SX08A-TQG100I-B1, EX128-PTQG100I-B4, EX128-TQG100-B4, EX128-TQG100I-B4, EX256-PTQG100I-B4, EX256-TQG100-B4 and EX256-TQG100I-B4 internal catalog part numbers (CPN). Provided estimated first ship date to be on June 30, 2025.
Description of Change: Qualification of Lead-Lock Tape for selected A54SX08A, EX256, and EX128 device families available in 100L LQFP (14x14x1.4mm) package.Reason for Change: To improve manufacturability by qualifying lead-lock tape.
PCN Status:Final NotificationDescription of Change:Release of updated software version of Synplify Pro Microchip Edition v2023.09M-1 & Synplify Pro Standalone v2023.09-1 for various FPGA devices.Reason for Change:Synplify Pro standalone all-vendor versions 2023.03 and 2023.09, as well as Microchip Edition version 2023.09M could incorrectly extract the enable signal logic during RTL synthesis when the signal path contains a set of multiplexors connected in series around a register, and the MUXs are driven by bus ports. This is described in the attached Customer Notice.
Description of Change:Release of updated Synplify Pro ME version S-2021.09M-SP2 FPGA synthesis software bundled with Libero SoC v2022.3Reason for Change:Release updated Synplify Pro ME version S-2021.09M-SP2 FPGA synthesis software bundled with Libero SoC v2022.3 to prevent incorrect Verilog mapping of RTL using increment/decrement operations (++ / --) while indexing into an array on the right-hand side (RHS) of an assignment statement, as described in the attached Customer Notice.
Description of Change:Release of updated Synplify Pro ME version S-2021.09M-SP2 synthesis software bundled with Libero SoC v2022.3 as described in the attached customer notification details.Reason for Change:Release updated Synplify Pro ME version S-2021.09M-SP2 synthesis software bundled with Libero SoC v2022.3 to prevent incorrect VHDL expression evaluation during compilation, when performing subtraction with a real constant number operand, and an additional division/multiplication operation that uses a variable. This is to fix a VHDL compiler issue that occurs in specific VHDL expressions.
Statut du produit:
Stock conservé dans l'entrepôt du fabricant. Sous réserve de disponibilité et de temps de transit.
