Microchip | SY89874UMG-TR

The SY89874UMG TR is a Differential In-to-LVPECL Programmable Clock Divider/ Fanout Buffer it is low-skew, low-jitter device capable of accepting a high-speed (e.g., 622 MHz or higher) CML, LVPECL, LVDS or HSTL clock input signal.

This device is available divider ratios are 2, 4, 8 and 16, or straight pass-through. In a typical 622MHz clock system this would provide availability of 311 MHz, 155 MHz, 77 MHz or 38 MHz auxiliary clock components.

Features:

• Integrated programmable clock divider and 1:2 fanout buffer
• Guaranteed AC performance over temperature and voltage:
  • > 2.5 GHz fMAX
  • < 250ps tr/tf
  • < 15ps within device skew
  • Low jitter design:
  • <10psPP total jitter
  • <1psRMS cycle-to-cycle jitter
• TTL/CMOS inputs for select and reset
• 100k EP compatible LVPECL outputs
• Parallel programming capability
• Programmable divider ratios of 1, 2, 4, 8 and 16
• Low voltage operation 2.5 V or 3.3 V
• Output disable function
• –40°C to 85°C temperature range
• Available in 16-pin (3mm × 3mm) MLF® package

Applications:

• SONET/SDH line cards
• Transponders
• High-end, multiprocessor sensors