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A42MX16-2PQG100I
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66 per Tray
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PCN Information:
*** Update for PCN112385/PCN112233/Location and Material Change****Description of Change: Qualification of ASEK as new assembly site for selected A40MX02, A40MX04, A42MX09 and A42MX16 device families available in 100L PQFP (14x20x2.7mm) package.Reason for Change: To improve manufacturability by qualifying ASEK as a new assembly site.Estimated First Ship Date: 30 September 2025 (date code: 2540)Revision History: April 05, 2025: Issued initial notification.April 11, 2025: Re-issued initial notification to update affected CPN list.September 04, 2025: Issued final notification. Attached the Qualification Report. Provided estimated first ship date to be on September 30, 2025.
PCN Status:Initial NotificationDescription of Change:Qualification of ASEK as new assembly site for selected A40MX02, A40MX04, A42MX09 and A42MX16 device families available in 100L PQFP (14x20x2.7mm) package.Reason for Change:To improve manufacturability by qualifying ASEK as a new assembly site.Change Implementation Status:In ProgressEstimated Qualification Completion Date:August 2025
PCN Status:Final NotificationDescription of Change:Release of updated software version of Synplify Pro Microchip Edition v2023.09M-1 & Synplify Pro Standalone v2023.09-1 for various FPGA devices.Reason for Change:Synplify Pro standalone all-vendor versions 2023.03 and 2023.09, as well as Microchip Edition version 2023.09M could incorrectly extract the enable signal logic during RTL synthesis when the signal path contains a set of multiplexors connected in series around a register, and the MUXs are driven by bus ports. This is described in the attached Customer Notice.
Description of Change:Release of updated Synplify Pro ME version S-2021.09M-SP2 FPGA synthesis software bundled with Libero SoC v2022.3Reason for Change:Release updated Synplify Pro ME version S-2021.09M-SP2 FPGA synthesis software bundled with Libero SoC v2022.3 to prevent incorrect Verilog mapping of RTL using increment/decrement operations (++ / --) while indexing into an array on the right-hand side (RHS) of an assignment statement, as described in the attached Customer Notice.
Description of Change:Release of updated Synplify Pro ME version S-2021.09M-SP2 synthesis software bundled with Libero SoC v2022.3 as described in the attached customer notification details.Reason for Change:Release updated Synplify Pro ME version S-2021.09M-SP2 synthesis software bundled with Libero SoC v2022.3 to prevent incorrect VHDL expression evaluation during compilation, when performing subtraction with a real constant number operand, and an additional division/multiplication operation that uses a variable. This is to fix a VHDL compiler issue that occurs in specific VHDL expressions.
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Inventory held at our manufacturer's warehouse. Subject to availability and transit time.
