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Manufacturer Part #
ATSAME54P19A-CTUT-EFP
ARM Cortex-M4F SAM E54 Microcontroller IC 32-Bit Single-Core 120MHz 512KB (512
Microchip ATSAME54P19A-CTUT-EFP - Product Specification
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PCN Status:End of Life (EOL) NotificationEOL Description:The ATSAMD51N20A-AZ, ATSAME51N19A-AU-EFP, ATSAME53J18A-AZ, ATSAME53J20A-MZ, ATSAME54P19A-AZ and ATSAME54P19A-CTUT-EFP catalog part numbers (CPN) will be moving to End of Life (EOL) status effective today. These catalog part numbers will no longer be offered after December 15, 2025. Please review the attached parts affected list below for the details about replacement parts if applicable.Note:If replacement parts are not listed in the attached list please contact your Local Sales RepresentativeReason for EOL:No longer have manufacturing support for the CPN listed in the attachment.Estimated Effective Dates:Customers affected by this EOL notice are advised to place last time buy (LTB) orders as follows:Last Date for Bookings (LTB): 15 June 2025Last Date for Shipments (LTS): 15 December 2025
Microchip has released a new Datasheet for the SAM D5x/E5x Family Data Sheet of devices.Notification Status: FinalDescription of Change:Section Name or TypeChange DescriptionFeatures? Added content for Related Devices to the Features setImpacts to Data Sheet: NoneReason for Change: To Improve Productivity Change Implementation Status: CompleteDate Document Changes Effective: 10 Dec 2024
Microchip has released a new Errata for the SAM D5x/E5x Family Silicon Errata and Data Sheet Clarification of devices.Notification Status: FinalDescription of Change: The following errata were added in this revision:? Device: 2.6.10 Power UpImpacts to Data Sheet: NoneChange Implementation Status: CompleteDate Document Changes Effective: 01 Mar 2023
Microchip has released a new Errata for the SAM D5x/E5x Family Silicon Errata and Data Sheet Clarification of devices.Notification Status: FinalDescription of Change: The following errata were added in this revision:? SERCOM: 2.18.26 SERCOM-USART LIN Host Delays? SERCOM: 2.18.27 SERCOM-USART Two Stop Bits in LIN Host The following errata were updated with new verbiage in this revision:? Device: Detection of a Debugger Probe 2.6.3? SUPC: Buck Converter Mode 2.19.1Impacts to Data Sheet: NoneChange Implementation Status: CompleteDate Document Changes Effective: 12 Dec 2022
Microchip has released a new Errata for the SAM D5x E5x Family Silicon Errata and Data Sheet Clarification of devices.Revision History:October 14, 2022: Updated "Date Document Change Effective" to "Estimated First Ship Date".Description of Change: The following updates were implemented in this revision along with numerous typographical corrections: ?Updated the silicon revision throughout the document to F ? Deprecated DAC errata for Smoothing of the Output Signal in Differential Mode The following errata were added in this revision: ? ADC: Internal Bandgap Reference 2.1.6 ? CAN: Transmit Cancellation 2.4.14 ? Device: Standby Mode 2.6.9 ? DAC: Refresh Mode 2.9.7 ? NVMCTRL: Debugger Illegal Accesses 2.14.3 ? TCC: STATUS Register Access 2.21.9 ? TCC: Sequence State 2.21.10 ? EVSYS: Synchronous/Resynchronized Modes 2.24.3 ? OSC32KCTRL: Clock Switch Back Feature Limitation 2.26.1 ? OSCCTRL: Clock Switch Back Feature Limitation 2.27.1 The following Data Sheet Clarifications were added in this revision: ? I/O Pins Maximum Output Current Table 54-1Reason for Change: To Improve Productivity
Microchip has released a new Errata for the SAM D5x E5x Family Silicon Errata and Data Sheet Clarification of devices.Description of Change: The following updates were implemented in this revision along with numerous typographical corrections: ?Updated the silicon revision throughout the document to F ? Deprecated DAC errata for Smoothing of the Output Signal in DifferentialMode The following errata were added in this revision: ? ADC: Internal Bandgap Reference 2.1.6 ? CAN: Transmit Cancellation 2.4.14 ?Device: Standby Mode 2.6.9 ? DAC: Refresh Mode 2.9.7 ? NVMCTRL: Debugger Illegal Accesses 2.14.3 ? TCC: STATUS Register Access2.21.9 ? TCC: Sequence State 2.21.10 ? EVSYS: Synchronous/Resynchronized Modes 2.24.3 ? OSC32KCTRL: Clock Switch Back FeatureLimitation 2.26.1 ? OSCCTRL: Clock Switch Back Feature Limitation 2.27.1 The following Data Sheet Clarifications were added in thisrevision: ? I/O Pins Maximum Output Current Table 54-1Reason for Change: To Improve Productivity
Microchip has released a new Product Documents for the SAM D5x/E5x Family Errata and Data Sheet Clarification of devices.Notification Status: FinalDescription of Change:? RTC: Tamper Detection 2.17.4 was updated with new Workaround information ? Terminology for ?Master,? and ?Slave,? was updated to ?Host,? and ?Client? respectively. This change may not be reflected in all associated Microchip Documentation. For more information, contact a Microchip Representative. ? Added the following Errata: ? 2.4.12 Transmit Message Order Inversion ? Device: Overconsumption in Standby 2.6.7 ? DFLL48M: Lose Lock After Wake Bit 2.8.7 ? RTC: Battery backup Mode 2.17.9 ? RTC: Active Layer Protection 2.17.10 ? 2.18.23 SERCOM-I2C: Automatic Acknowledge ? TC: PER Register (8-bit mode) 2.20.3 ? PDEC: Counter Operating Mode 2.22.3 ? PDEC: Counter Operating Mode 2.22.4 ? 2.22.5 Direction Change ? 2.22.6 Hall Mode ? 2.22.7 Hall Mode ? 2.22.8 Error Flags Impacts to Data Sheet: NoneReason for Change: To Improve ProductivityChange Implementation Status: CompleteDate Document Changes Effective: 16 Jun 2021NOTE: Please be advised that this is a change to the document only the product has not been changed.
Microchip has released a new Product Documents for the SAM D5x/E5x Family Errata and Data Sheet Clarification of devices. Notification Status: FinalDescription of Change: The errata had updates to their titles for clarification.Impacts to Data Sheet: NoneReason for Change: To Improve ProductivityChange Implementation Status: CompleteDate Document Changes Effective: 11 Jan 2021NOTE: Please be advised that this is a change to the document only the product has not been changed.
Microchip has released a new Product Documents for the SAM D5X/E5X Family Datasheet of devices. If you are using one of these devices please read the document attached located at SAM D5X/E5X Family Datasheet.Notification Status: FinalDescription of Change:1) General: Along with the updates listed below, numerous typographical and minor editorial updates were made to this document.2) Features: Updated Memories to show proper nomenclature for SmartEEPROM.3) Configuration Summary: Updated Table 1-2 with new I2S specs for SAME51G18 and SAME51G19.4) I/O Multiplexing and Considerations: Updated Table 6-34 GPIO Clusters, removed erroneous GPIO designations for the 100 pin package.5) Memories: Updated Table 9-4 for bit position 75:64.6) CMCC: Removed erroneous bitfields from the TYPE Register.7) DSU:- Updated SmartEEPROM nomenclature in Chip Erase- Updated references to SmartEEPROM in Table 12-3 of 32-bit Cyclic Redundancy Check CRC32- Updates table 12-6 in System Services Availability when Accessed Externally and Device is Protected with proper verbiage for SmartEEPROM- Updated ENTRY0 and ENTRY1 registers with correct numbering8) Clock System: Updated the Clock Request Routing Diagram in On Demand Clock Requests.9) GCLK: Updated the GENCTRLn register with a new bitfield length for the SRC bit, and added new data to the end of table 14-4 Generator Clock Source Selection.10) MCLK:- Updated the table in Peripheral Clock Masking with new values for the ADC, NVMCTRL, and removed a reference to the PTC- Updated the bitfield numbering and reset values in the following registers:? AHBMASK? APBCMASK11) PM:- Updated figure 18-2 in Sleepwalking- Updated the register offset for the PWSAKDLY Register12) SUPC: Removed an erroneous BOD12 reference from Enabling, Disabling, and Resetting.13) RTC: Updated the COUNT32 Register with a new note.14) DMAC: Updated the following registers with new bitfield verbiage:- BASEADDR- WRBADDR- SRCADDR- DSTADDR15) GMAC- Updated the following registers with new bitfield information for bit 27:ISRIERIDRIMR- Updated the TPB1ADR bit in the TPSF Register- Updated the RPB1ADR bit in the RPSF Register- Added the TPFCP Register- Renamed the bitfield in the TLPITI Register from RLPITI to TLPITI16) NVMCTRL- Updated verbiage for SmartEEPROM throughout the entire chapter- Corrected typographical errors in Safe Flash Update Using Dual Banks- Updated the CELCK Description in the table for the CMD bit in the CTRLB Register17) ICM: Updated the Functional Description Overview topic with new verbiage for the end of list marker and WRAP bitsetting.18) OSCCTRL: Updated references for the SWBCK bit to the SWBEN bit in the Clock Switch section of Clock FailurDetection Operation.19) OSC32KCTRL:- Added a new note to 32 kHz Ultra Low-Power Internal Oscillator (OSCULP32K) Operation, and removed erroneous text references to the CALIB bit- Updated the OSCULP32K Register with the removal of the erroneous CALIB bit, and converted it to a Reserved bit 20) EVSYS:- Updated the following registers with new bitfield numbering:CHANNELUSERm21) PORT: Updated the bitfield numbering for the PORTEIx, EVACTx, and PIDx bits in the EVCTRL Register.22) SERCOM I2C:- Corrected references for the LOWTOUTEN bit in Initialization- Updated the CTRLA (Slave) Register with corrections to the name for the LOWTOUTEN bit- Added a new LENERR bit to the STATUS (Slave) Register- Updated the CTRLA (Master) Register with corrections to the name for the LOWTOUTEN bit23) QSPI:- Updated Serial Clock Phase and Polarity with new values for the Capture SCK Edge column in table 37-2- Added a new note to QSPI Serial Memory Mode- Updated the bitfield Access for the ENABLE bit in the CTRLA Register24) USB: The STATUS (Device Registers - Common) was updated with new bitfield data.25) CAN: Updates were made to the following Registers for bitfield naming, numb
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