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Manufacturer Part #
ATSAML10D14A-MU
SAML10: 16KB Flash 4KB SRAM 32MHz ARM Cortex-M23 32-Bit Microcontroller-VQFN-24
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| Mfr. Name: | Microchip | ||||||||||
| Standard Pkg: | Product Variant Information section Available PackagingPackage Qty:490 per Tray Package Style:VQFN-24 Mounting Method:Surface Mount | ||||||||||
| Date Code: | |||||||||||
Product Specification
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PCN Information:
Microchip has released a new Product Documents for the SAM L10/L11 Family Silicon Errata and Data Sheet Clarification of devices.Notification Status: FinalDescription of Change: The SPI, I2S, and I2C standards use the terminology "Master" and "Slave". The equivalent Microchip terminology used in this document is "Host" and "Client" respectively. These terms have been updated throughout this document for this revision.This revision contains numerous typographical updates, and formatting updates.Obsolete Data Sheet Clarifications have been removed in this update.The following errata were added in this revision:• RTC: 2.9.12 Active Layer Protection• SERCOM I2C: 2.10.11 Automatic Acknowledge• TC: 2.13.4 PER register (8-bit mode)• EVSYS: 2.18.3 Spurious Overrun• EVSYS: 2.18.4 Software Event• EVSYS: 2.18.5 PAC Write-Protection• OSCCTRL: 2.19.4 FDPLL96M On Demand in Standby• OSCCTRL: 2.19.5 DFLLULP Dithering ModeNVMCTRL: 2.22.1 Data FLASH Silent Access and ScramblingImpacts to Data Sheet: NoneReason for Change: To Improve ProductivityChange Implementation Status: CompleteDate Document Changes Effective: 15 Jul 2021NOTE: Please be advised that this is a change to the document only the product has not been changed.Markings to Distinguish Revised from Unrevised Devices: N/A
Microchip has released a new Product Documents for the SAM L10/L11 Family Data Sheet of devices.Notification Status: Final Description of Change: The following additions or updates were done during this revision:1. General1.1 Throughout the entire document all references of “Master” were changed to “Host,” and “Slave” was changed to “Client,” where applicable1.2 Previous Revision histories were consolidated to clean up the flow of the document2. Features - Added new information for PWM Modes using TC peripherals.3. Analog Peripherals Consideration - Updated the note for Caution, and the Analog Signal Components Interconnections Diagram4. Memories4.1 Updated Flash with a new Caution note4.2 Updated Data Flash with a new Caution note5. SAM L11 Specific Security Features - Added two new figures to SAM L11 Memory Mapping Configuration Summary:5.1 SAM L11 Default Memories Mapping - 64KB Flash Case5.2 SAM L11 Default Memories Mapping - 16/32KB Flash Case6. Clock System - Updated the figure in On Demand Clock Requests to read CHEN instead of CLKEN7. MCLK7.1 Updated Clock Ready Flag with text regarding the CPUDIV value7.2 Updated the INTFLAG Register with new text for the CKRDY bitfield8. FREQM8.1 Updated the Block Diagram. CLK_REF is now CLK_REF_MUX8.2 Updated CLK_REF to read CLK_REF_MUX in Principle of Operation8.3 Updated CLK_REF to read CLK_REF_MUX in Measurement9. PM9.1 Added all new text and a new caution note to SRAM Power Switch Configuration9.2 Added a caution note to the PWCFG Register, and updated the existing KB Flash tables and added new tables for 32KB and 16KB9.3 Corrected a typographical error in the INTFLAG Register10. OSCCTRL10.1 An important note was added to External Multipurpose Crystal Oscillator (XOSC) Operation10.2 An important note was added to Clock Failure Detection Operation10.3 Replaced text in the last paragraph of Initialization, Enabling, Disabling, and Resetting10.4 Updated the XOSCCTRL Register with new text and note for the STARTUP Bitfield11. OSC32KCTRL11.1 Updated Overview with new text11.2 Updated 32KHz External Crystal Oscillator (XOSC32K) Operation with a new important note11.3 Added new text and an important note to Clock Failure Detection Operation11.4 Updated bitfield descriptions in the following registers with new important notes, and new text:11.4.1 RTCCTRL11.4.2 XOSC32K12. RTC - Updated the following registers with new notes:12.1 COUNT (COUNT32)12.2 COUNT (COUNT16)13. DMAC - Updated the following registers with new bit alignment values:13.1 BASEADDR13.2 WRBADDR13.3 DESCADDR14. PORT - Updated the figure in the Functional Description15. EVSYS - Updated Sleep Mode Operation with a new note and a new row to the Event Channel Sleep Behavior Table16. SERCOM - Updated I/O Lines with new text17. SERCOM USART17.1 Updated I/O Lines with new text17.2 Updated the bit description for the MAXITER bit in the CTRLC Registe18. SERCOM SPI 18.1 Updated I/O Lines with new text18.2 Updated the DOPO bitfield with new text in the CTRLA Register19. SERCOM I2C19.1 Updated I/O Lines with new text19.2 Updated the CTRLB Register with new bitfield access values for the CMD and QCEN bitfields20. TC20.1 Updated Capture Operations with new notes20.2 Updated Event Capture Action to read Event Capture Action on Events or I/Os, added new text and corrected capitalization in the diagram20.3 Updated Period and Pulse-Width (PPW) Capture Action to read Period and Pulse-Width (PPW/PWP) Capture Action on Events, and updated capitalization in the diagram20.4 Updated Pulse Width Capture Action to read Pulse-Width (PW) Capture Action on Events, and updated the capitalization in the diagram20.5 Updated Time Stamp Capture to read Time-Stamp Capture on Events or I/Os and removed the term Capture from the diagram20.6 Removed non-applicable text from Events20.7 Added new notes to the following registers:2
PCN Status: Final notificationPCN Type: Manufacturing ChangeDescription of Change:Qualification of MMT as an additional assembly site for selected Atmel ATSAML10D1xA, ATSAML11D1xA, ATSAMD11D14A, ATSAMD10D1xA, ATSAMD09D14A and ATMPS001D14A device families available in 24L VQFN (4x4x0.9mm) package.Impacts to Data Sheet: Yes. Package Outline Drawing (POD)Change Impact:NoneReason for Change:To improve on-time delivery performance by qualifying MMT as an additional assembly site.Change Implementation Status:In ProgressEstimated First Ship Date:May 28, 2021 (date code: 2122)
Microchip has released a new Product Documents for the SAM L10/L11 Family Silicon Errata and Data Sheet Clarification of devices. If you are using one of these devices please read the document attached located at SAM L10/L11 Family Silicon Errata and Data Sheet Clarification.Notification Status: FinalDescription of Change: This revision contains numerous typographical updates, and formatting updates.The following errata were updated with new verbiage:DMAC: 2.4.1 Concurrent Channels TriggerEIC: 2.5.1 PAC ProtectionOPAMP: 2.8.1 Reference BufferSERCOM I2C: 2.10.8 Status FlagsSERCOM I2C: 2.10.9 Status FlagsSERCOM SPI: 2.11.1 Data PreloadSERCOM USART: 2.12.5The following errata were added in this revision:ADC: 2.1.2 Offset CorrectionDevice: 2.3.2 Standby EntryRTC: 2.9.9 Tamper DetectionRTC: 2.9.10 Tamper DetectionRTC: 2.9.11 General Purpose RegistersSERCOM I2C: 2.10.10 Status FlagsSERCOM SPI: 2.11.2 Hardware Slave Select ControlSERCOM SPI: 2.11.3 Slave Data PreloadSERCOM SPI: 2.11.4 Wakeup InterruptSERCOM USART: 2.12.6 Overconsumption in Standby ModeSERCOM USART: 2.12.7 Wakeup InterruptTC: 2.13.3 RetriggerOSC32KCTRL: 2.16.2 1024 Hz Clock OutputOSC32KCTRL: 2.16.3 Clock Failure DetectionOSC32KCTRL: 2.16.4 XOSC32K Ready BitEVSYS: 2.18.1 Synchronous and Resynchronized ModesEVSYS: 2.18.2 Synchronous ModeOSCCTRL: 2.19.1 Clock Failure DetectionOSCCTRL: 2.19.2 Clock Failure DetectionOSCCTRL: 2.19.3 XOSC Ready BitPORT: 2.20.1 IOBUSTRAM: 2.21.1 PAC ProtectionImpacts to Data Sheet: NoneReason for Change: To Improve Productivity Change Implementation Status: Complete Date Document Changes Effective: 08 Jan 2021NOTE: Please be advised that this is a change to the document only the product has not been changed.Markings to Distinguish Revised from Unrevised Devices: N/A
Microchip has released a new Product Documents for the SAM L10/L11 Family Data Sheet of devices. Notification Status: Final Description of Change: In addition to the changes listed in the following table, there were numerous typographical updates that were made throughout the document.The following additions or updates were done during this revision� Features� Configuration Summary� Pinout� Memories� SAM L11 Specific Security Features� Boot ROM� DSU� MCLK� FREQM� DMAC� NVMCTRL� TRAM� SERCOM� SERCOM I2C- TC� TRNG� ADC� OPAMP� Electrical Characteristic at 85?C� Electrical Characteristic at 125?C� AEC-Q100 Grade Electrical CharacteristicsImpacts to Data Sheet: NoneReason for Change: To Improve ProductivityChange Implementation Status: CompleteDate Document Changes Effective: 26 Jun 2020NOTE: Please be advised that this is a change to the document only the product has not been changed.
Microchip has released a new DeviceDoc for the SAM L10/L11 Family Data Sheet of devicesDescription of Change: Updated the following sections:1. Features2. Ordering Information3. Memories4. Processor and Architecture5. Peripherals Configuration Summary6. SAM L11 Specific Security Features7. Peripheral Access Controller8. GCLK9. MCLK10. FREQM11. PM12. OSCCTRL13. OSC32KCTRL14. SUPC15. WDT16. RTC17. DMAC18. EIC19. NVMCTRL20. TRAM21. PORT - I/O Pin Controller22. EVSYS23. SERCOM24. SERCOM - USART25. SERCOM - SPI26. SERCOM I2C27. TC28. TRNG29. CCL30. ADC31. AC32. DACReason for Change: To Improve ManufacturabilityPlease be advised that this is a change to the document only the product has not been changed.
ERRATA - SAM L10/L11 Family Silicon Errata and Data Sheet ClarificationMicrochip has released a new DeviceDoc for the SAM L10/L11 Family Silicon Errata and Data Sheet Clarification of devices.Description of Change: The following new errata were added to: 1) RTC section: 2.9.5 Prescaler Reference: TMR102-52, 2.9.6 Active Layer Protection Reference: TMR102-66, 2.9.7. Tamper Detection Timestamp Reference: TMR102-67 and 2.9.8 Tamper Detection Timestamp Reference: TMR102-60. 2) SERCOM USART section: 2.12.5 Wakeup Reference: COM100-41Reason for Change: To Improve ProductivityPlease be advised that this is a change to the document only the product has not been changed
Microchip has released a new DeviceDoc for the SAM L10/L11 Family Silicon Errata and Data Sheet Clarification of devices.Description of Change:The following new errata were added:- RTC: 2.9.4 Tamper Detection Timestamp- SUPC: 2.15.1 Buck Converter Mode- OSC32KCTRL: 2.16.1 External 32.768KHz Crystal Oscillator- Boot ROM: 2.17.1 GCM APIThe following errata is updated:- ADC: 2.1.1 Reference Buffer Offset CompensationThe following Data Sheet clarifications were added:Updates to Electrical Specifications Tables: a) Table 46-8, b) Table 46-54, c) Table 47-2Reason for Change: To Improve ProductivityDate Document Changes Effective: 19 Feb 2019NOTE: Please be advised that this is a change to the document only the product has not been changed.
Microchip has released a new DeviceDoc for the SAM L10/L11 Family Data Sheet of devices.Description of Change:1) Configuration Summary - Updated SAML10/L11 Family Features2) Oscillators Pinout - Updated XOSC32 Jitter Minimization3) Memories- Updated NVM Software Calibration Bitfields Definition- Updated SAM L11 BOCOR Bitfields Definition- Updated SAM L11 BOCOR Mapping4) 13.1 Features- Updated Features- Updated CRYA APIs Addresses with a note5) Boot ROM- Updated Secure Boot Options- Updated Accessible Memory Range by Read Auxiliary Row Command, and added a note6) Device Service Unit (DSU) - Updated STATUSB Register7) Power Manager (PM) - Updated PLCFG Register8) Oscillators Controller (OSCCTRL)- Corrected missing Block Diagram- Updated the reset value for the STATUS Register9) 32KHz Oscillators Controller (OSC32KCTRL) - Updated the ULP32KSW bit in the OSCULP32K Register10) Supply Controller (SUPC) - Corrected erroneous text and added a note to Low Power VREF in Active Mode11) Real Time Counter (RTC)- Updated RTC Block Diagram (Tamper Detection Use Case)- Updated Active Layer Protection- Updated TAMPCTRL Register with new notes for the DEBNC and TAMLVL bits- Updated TAMPCTRLB Register with a note for the ALSI bits12) Direct Memory Access Controller (DMAC)- Updated the text for the DMAC Clocks section- Updated the LVLEN bits for the CRTL Register- Updated the LVLEX bits for the ACTIVE Register13) External Interrupt Controller (EIC)- Updated the NMIFLAG Register- Updated the CONFIG Register to reflect changes to the FILTEN and SENSE bits14) Nonvolatile Memory Controller (NVMCTRL)- Corrected erroneous text in Cache- Corrected table entries in Memory Regions AHB Access Limitations and an updated a note.- Updated Data Flash Scrambling15) TrustRAM (TRAM)- Corrected Erroneous text in Overview- Updated Features16) I/O Pin Controller (PORT) - Updated the PORTEI, EVACT, and PID bits in the EVCTRL Register17) Event System (EVSYS) - Corrected text in Initialization18) SERCOM USART- Updated the BAUD Register- Updated the equation in the RXPL Register19) SERCOM I2C- Updated Signal Description- Updated the property for the slave DATA Register- Updated the master DATA Register20) Timer/Counter (TC)- Updated the MCEO bits in the EVCTRL Register for 8-bit, 16-bit and 32-bit Modes- Updated The MC Bits in the INTENCLR, INTENSET, and INTFLAG Registers for 8-bit, 16-bit and 32-bit Modes- Updated the CCBUFV bit in the STATUS Register for 8-bit, 16-bit and 32-bit Modes- Updated the INVEN Bit in the DRVCTRL Register for 8-bit, 16-bit and 32-bit Modes21) Configurable Custom Logic (CCL)- Updated text in Overview- Updated the Block Diagram- Updated the table in Signal Description- Updated Linked LUT- Updated Analog Comparator Inputs- Removed erroneous TCC text- Updated the INSEL bits in the LUTCTRL0 Register- Updated the INSEL bits in the LUTCTRL1 Register22) Analog-to-Digital Converter (ADC)- Updated Features- Updated the Block Diagram- Updated the text in ADC Resolution- Added a note in Oversampling and Decimation- Updated the CTRLC Register23) Analog Comparators (AC)- Updated the text in VDD Scaler- Updated the START bits in the CTRLB Register- Updated the COMPEO, COMPEI, and INVEI bits in the EVCTRL Register- Updated the COMP bits in the INTENCLR, INTENSET, and INTFLAG Registers- Updated the STATE bits in the STATUSA Register- Updated the READY bits in the STATUSB Register- Updated the COMPCTRL bits in the SYNCBUSY Register24) Digital-to-Analog Converter (DAC)- Updated Features- Updated Dithering Mode25) Operational Amplifier Controller (OPAMP)- Updated the diagram in 44.6.11.3 Offset Compensation- Updated the READY bits of the STATUS Register26) Electrical Characteristics- Updated the note in Absolute Maximum Ratings- Removed erroneous data from the External Components Requirements
Description of Change: 1) Initial release.Microchip has released a new DeviceDoc for the SAM L10/L11 Family Silicon Errata and Data Sheet Clarification of devices. Reason for Change: To Improve ProductivityDate Document Changes Effective: 25 Jun 2018NOTE: Please be advised that this is a change to the document only the product has not been changed.
Part Status:
Technical Attributes
| Package Style: | VQFN-24 |
| Mounting Method: | Surface Mount |
Available Packaging
Package Qty:
490 per Tray
Package Style:
VQFN-24
Mounting Method:
Surface Mount