onsemi | MC10EP32DTG

The MC10EP32 is an integrated divide by 2 divider with differential CLK inputs. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 µF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.

The reset pin is asynchronous and is asserted on the rising edge. Upon power-up, the internal flip-flops will attain a random state; the reset allows for the synchronization of multiple EP32’s in a system. The 100 Series contains temperature compensation.

Key Features:

• 350 ps Typical Propagation Delay
• Maximum Frequency > 4 GHz Typical (Figure 3)
• PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V
• NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -5.5 V
• Open Input Default State
• Safety Clamp on Inputs
• Q Output Will Default LOW with Inputs Open or at VEE
• Pb-Free Packages are Available

Applications:

• Reduce System clock skew over the alternative CMOS and TTL technologies.

Learn more about the MC10EP3x Family of Timing Solutions