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NXP | PCA9512ADP,118

Manufacturer Part #

PCA9512ADP,118

PCA9512A Series 5.5 V 400 kHz Hot Swappable I2C-bus and SMBus Buffer - TSSOP-8

ECAD Model:
Mfr. Name: NXP
Standard Pkg:
Product Variant Information section
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Product Specification Section
NXP PCA9512ADP,118 - Technical Attributes
Attributes Table
Interface Type: I2C/SMBus
No of Channels: 2
Clock Frequency-Max: 400kHz
Supply Voltage-Nom: 2.7V to 5.5V
Supply Current: 1.8mA
Package Style:  TSSOP-8
Mounting Method: Surface Mount
Features & Applications

The PCA9512A/B is a hot swappable I²C-bus and SMBus buffer that allows I/O card insertion into a live backplane without corruption of the data and clock buses and includes two dedicated supply voltage pins to provide level shifting between 3.3 V and 5 V systems while maintaining the best noise margin for each voltage level. Either pin may be powered with supply voltages ranging from 2.7 V to 5.5 V with no constraints on which supply voltage is higher. Control circuitry prevents the backplane from being connected to the card until a stop bit or bus idle occurs on the backplane without bus contention on the card. When the connection is made, the PCA9512A/B provides bidirectional buffering, keeping the backplane and card capacitances isolated.
 

The PCA9512A or PCA9512B can be used if the rise of VCC and VCC2 is simultaneous, but only the PCA9512B shall be used if the interval between rise of VCC and VCC2 is not simultaneous.

Features and benefits:

  • Bidirectional buffer for SDA and SCL lines increases fan-out and prevents SDA and SCL corruption during live board insertion and removal from multipoint backplane systems
  • Compatible with I²C-bus Standard mode, I²C-bus Fast mode, and SMBus standards
  • Built-in ΔV/Δt rise time accelerators on all SDA and SCL lines (0.6 V threshold) with ability to disable ΔV/Δt rise time accelerator through the ACC pin for lightly loaded systems, requires the bus pull-up voltage and respective supply voltage (VCC or VCC2) to be the same
  • 5 V to 3.3 V level translation with optimum noise margin
  • High-impedance SDAn and SCLn pins for VCC or VCC2 = 0 V
  • 1 V precharge on all SDAn and SCLn pins
  • Supports clock stretching and multiple master arbitration and synchronization
  • Operating power supply voltage range: 2.7 V to 5.5 V
  • 0 Hz to 400 kHz clock frequency

 

Pricing Section
Global Stock:
0
USA:
0
On Order:
0
Factory Stock:Factory Stock:
-1
Factory Lead Time:
16 Weeks
Minimum Order:
2500
Multiple Of:
2500
Total
$3,475.00
USD
Quantity
Unit Price
2,500+
$1.39
Product Variant Information section