NXP | PCA9575PW2,118

It is a CMOS device that provides 16 bits of General Purpose parallel Input/Output (GPIO) expansion in low voltage processor and handheld battery powered mobile applications and was developed to enhance the NXP family of I2C-bus I/O expanders.

Features and benefits:

• Separate supply rails for core logic and each of the two I/O banks provides voltage level shifting
• 1.1 V to 3.6 V operation with level shifting feature
• Very low standby current: < 2 uA
• 16 configurable I/O pins organized as 2 banks that default to inputs at power-up
• Outputs:
  • Totem pole: 1 mA source and 3 mA sink
  • Independently programmable 100 kΩ pull-up or pull-down for each I/O pin
  • Open-drain active LOW interrupt (1) output pin allows monitoring of logic level change of pins programmed as inputs
• Inputs:
  • Programmable bus hold provides valid logic level when inputs are not actively driven
  • Programmable Interrupt Mask Control for input pins that do not require an interrupt when their states change or to prevent spurious interrupts default to mask at power-up
  • Polarity Inversion register allows inversion of the polarity of the I/O pins when read
• 400 kHz I²C-bus serial interface
• Compliant with I²C-bus Standard-mode (100 kHz)
• Active LOW reset (1) input pin resets device to power-up default state
• GPIO All Call address allows programming of more than one device at the same time with the same parameters
• 16 programmable slave addresses using 4 address pins (28-pin TSSOP only)
• ESD protection exceeds 6000 V HBM per JESD22-A114, 500 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101
• Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA
• Packages offered: TSSOP28, TSSOP24, HWQFN24

Applications:

• Cell phones
• Media players
• Multi-voltage environments
• Battery operated mobile gadgets
• Motherboards
• Servers
• RAID systems
• Industrial control
• Medical equipment
• PLCs
• Gaming machines
• Instrumentation and test measurement