Microchip | SY89875UMG

The SY89875UMG is a 2.5 GHz low-skew, low-jitter device is capable of accepting a high-speed (e.g., 622 MHz or higher) CML, LVPECL, LVDS or HSTL clock input signal and dividing down the frequency using a programmable divider to create a lower speed version of the input clock

The differential input buffer has a unique internal termination design that allows access to the termination network through a VT pin. This feature allows the device to easily interface to different logic standards

Features:

• Integrated programmable clock divider and 1:2 fanout buffer
• Guaranteed AC performance over temperature and voltage:
  • > 2.0 GHz fMAX
  • < 200ps tr/tf
  • < 15ps within device skew
• Low jitter design:
  • <10psPP total jitter
  • <1psRMS cycle-to-cycle jitter
• LVDS compatible outputsa
• TTL/CMOS inputs for select and reset
• Parallel programming capability
• Programmable divider ratios of 1, 2, 4, 8 and 16
• Low voltage operation 2.5 V
• Output disable function
• –40°C to 85°C temperature range

Applications:

• SONET/SDH line cards
• Transponders
• High-end, multiprocessor servers