
Manufacturer Part #
LPC1786FBD208,551
LPC17xx Series 512 kB Flash 96 kB RAM SMT 32-Bit-Microcontroller - LQFP-208
| |||||||||||
Mfr. Name: | NXP | ||||||||||
Standard Pkg: | Product Variant Information section Available PackagingPackage Qty:36 per Tray Package Style:LQFP-208 Mounting Method:Surface Mount | ||||||||||
Date Code: |
Product Specification
Shipping Information:
ECCN:
PCN Information:
Product Lifecycle:
Technical Attributes
Family Name: | LPC17xx |
Core Processor: | ARM Cortex M3 |
Program Memory Type: | Flash |
Flash Size (Bytes): | 512kB |
RAM Size: | 96kB |
Speed: | 100MHz |
No of I/O Lines: | 165 |
InterfaceType / Connectivity: | Ethernet/I2C/I2S/LCD Graphic Controller/SPI/SSP/UART/USB |
Peripherals: | Ethernet/I2C/I2S/On-Chip-ADC/PWM/SPI/SSP/UART/USB/Watchdog |
Number Of Timers: | 4 |
Supply Voltage: | 2.4V to 3.6V |
Operating Temperature: | -40°C to +85°C |
On-Chip ADC: | 8-chx12-bit |
Watchdog Timers: | 1 |
Package Style: | LQFP-208 |
Mounting Method: | Surface Mount |
Features & Applications
The Cortex-M3 is a next generation core that offers better performance than the ARM7 at the same clock rate and other system enhancements such as modernized debug features and a higher level of support block integration. The Cortex-M3 CPU incorporates a 3-stage pipeline and has a Harvard architecture with separate local instruction and data buses, as well as a third bus with slightly lower performance for peripherals. The
Cortex-M3 CPU also includes an internal prefetch unit that supports speculative branches.
The LPC178x/7x adds a specialized flash memory accelerator to accomplish optimal performance when executing code from flash. The LPC178x/7x is targeted to operate at up to 100 MHz CPU frequency.
Features and Benefits:
- Functional replacement for LPC23xx and 24xx family devices
- System:
- ARM Cortex-M3 processor, running at frequencies of up to 100 MHz. A Memory Protection Unit (MPU) supporting eight regions is included
- ARM Cortex-M3 built-in Nested Vectored Interrupt Controller (NVIC)
- Multilayer AHB matrix interconnect provides a separate bus for each AHB master. AHB masters include the CPU, and General Purpose DMA controller. This interconnect provides communication with no arbitration delays unless two masters attempt to access the same slave at the same time
- Split APB bus allows for higher throughput with fewer stalls between the CPU and DMA. A single level of write buffering allows the CPU to continue without waiting for completion of APB writes if the APB was not already busy
- Memory:
- 512 kB on-chip flash program memory with In-System Programming (ISP) and In-Application Programming (IAP) capabilities. The combination of an enhanced flash memory accelerator and location of the flash memory on the CPU local code/data bus provides high code performance from flash
- 4 kB on-chip EEPROM
- LCD controller, supporting both Super-Twisted Nematic (STN) and Thin-Film Transistors (TFT) displays
- Dedicated DMA controller
- Selectable display resolution (up to 1024 × 768 pixels)
- Supports up to 24-bit true-color mode
- External Memory Controller (EMC) provides support for asynchronous static memory devices such as RAM, ROM and flash, as well as dynamic memories such as single data rate SDRAM
- Serial interfaces
- Digital peripherals
- Analog peripherals
- Power control
- Clock generation
- Versatile pin function selection feature allows many possibilities for using on-chip pheripheral functions
- Unique device serial number for identification purposes
- Single 3.3 V power supply (2.4 V to 3.6 V). Temperature range of −40 °C to 85 °C
- Available as LQFP208, TFBGA208, TFBGA180, and LQFP144 package
Available Packaging
Package Qty:
36 per Tray
Package Style:
LQFP-208
Mounting Method:
Surface Mount