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A40MX02-PLG68I
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19 per Tube
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Description of Change: Qualification of 3280NP as an additional die attach material for selected PIC16Cxx, PIC17Cxx, PIC18Fxx, PIC18Cxx, A40MX0xx, AT89C5xx, TC7117xx, TC7106xx, TC7107xx, TC850xx, TC7116xx, TC7109xx, PIC16Fxx, AY0438xx, HV518xx, HV5222xx, HV5308xx, HV9308xx, HV9408xx, HV5408xx, TC7129xx, MM5450xx, MM5451xx, ATF150xx, AT80C5xx, AT89LPxx, AT89S5xx, AT89LSxx, AT89S8xx, ATF250xx, AT27BVxx, AT27C2xx, MT8812xx, MT8816xx, MT093xx, HV5122xx, AT27C1xx, AT27C4xx, HV5622xx, HV5630xx, LE58QLxx, ATmega8515, ATF16Lxx, AT17LVxx, ATF16Vxx, TC1443xx, HV5812xx, HV2022xx, HV2301xx, HV2201xx, HV219xx, ATF22Vxx, ATF750xx, MIC58Pxx, MIC59Pxx, MIC580xx, ATF22Lxx, SY100Exx, MT8952xx, MT9171xx, MT9172xx, MT9122xx, MT8808xx, MT8806xx, COM200xx, A42MX2xx, A42MX0xx, A42MX1xx, AT27C0xx, AT27LVxx, AT28C0xx, AT28LVxx, AT28HCxx, AT28C2xx, AT28BVxx, AT28C6xx, AT27C5xx, SST39Sxx, SST39Lxx, SST39Vxx, SST49Lxx and LE79R7xx device families available in various packages.Reason for Change: To improve manufacturability by qualifying 3280NP as an additional die attach material.Change Implementation Status: In ProgressEstimated Qualification Completion Date: June 2026
Description of Change:Implementation of Inner Box, Reel and MSL Bag Label changes for virtually ALL Microchip products.Reason for Change:To improve productivity by implementing inner box, reel and MSL bag label changes.
Description of Change: Qualification of MMT as a new assembly site for selected A40MX02 and A40MX04 device families available in 44L PLCC (16.6x16.6x4.4mm) and 68L PLCC (24.2x24.2x4.4mm) packages.Reason for Change: To improve on-time delivery performance by qualifying MMT as a new assembly site.
PCN Status:Final NotificationDescription of Change:Release of updated software version of Synplify Pro Microchip Edition v2023.09M-1 & Synplify Pro Standalone v2023.09-1 for various FPGA devices.Reason for Change:Synplify Pro standalone all-vendor versions 2023.03 and 2023.09, as well as Microchip Edition version 2023.09M could incorrectly extract the enable signal logic during RTL synthesis when the signal path contains a set of multiplexors connected in series around a register, and the MUXs are driven by bus ports. This is described in the attached Customer Notice.
Description of Change:Qualification of MMT as a new assembly site for selected A40MX02 and A40MX04 device families available in 44L (16.6x16.6x4.4mm) and 68L (24.2x24.2x4.4mm) PLCC packages.Reason for Change:To improve on-time delivery by qualifying MMT as a new assembly site.
Description of Change:Qualification of MTAI as an additional final test site for PM6104B-FEI, PM6108B-FEI and PM6110B-FEI catalog part numbers (CPN) available in 1221L BBGA (29x29x3.57mm) package.Reason for Change:To improve manufacturability and on-time delivery performance by qualifying MTAI as a new final test site.
Description of Change:Release of updated Synplify Pro ME version S-2021.09M-SP2 FPGA synthesis software bundled with Libero SoC v2022.3Reason for Change:Release updated Synplify Pro ME version S-2021.09M-SP2 FPGA synthesis software bundled with Libero SoC v2022.3 to prevent incorrect Verilog mapping of RTL using increment/decrement operations (++ / --) while indexing into an array on the right-hand side (RHS) of an assignment statement, as described in the attached Customer Notice.
Description of Change:Release of updated Synplify Pro ME version S-2021.09M-SP2 synthesis software bundled with Libero SoC v2022.3 as described in the attached customer notification details.Reason for Change:Release updated Synplify Pro ME version S-2021.09M-SP2 synthesis software bundled with Libero SoC v2022.3 to prevent incorrect VHDL expression evaluation during compilation, when performing subtraction with a real constant number operand, and an additional division/multiplication operation that uses a variable. This is to fix a VHDL compiler issue that occurs in specific VHDL expressions.
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