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Manufacturer Part #
A3PE3000L-1FGG324
ProASIC3EL Series 3000000 System Gate 1.575 V Surface Mount FPGA - FPBGA-324
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| Mfr. Name: | Microchip | ||||||||||
| Standard Pkg: | Product Variant Information section Available PackagingPackage Qty:84 per Tray | ||||||||||
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Microchip A3PE3000L-1FGG324 - Product Specification
Shipping Information:
ECCN:
PCN Information:
PCN Status:Final NotificationDescription of Change:Release of updated software version of Synplify Pro Microchip Edition v2023.09M-1 & Synplify Pro Standalone v2023.09-1 for various FPGA devices.Reason for Change:Synplify Pro standalone all-vendor versions 2023.03 and 2023.09, as well as Microchip Edition version 2023.09M could incorrectly extract the enable signal logic during RTL synthesis when the signal path contains a set of multiplexors connected in series around a register, and the MUXs are driven by bus ports. This is described in the attached Customer Notice.
Description of Change:Release of updated Synplify Pro ME version S-2021.09M-SP2 FPGA synthesis software bundled with Libero SoC v2022.3Reason for Change:Release updated Synplify Pro ME version S-2021.09M-SP2 FPGA synthesis software bundled with Libero SoC v2022.3 to prevent incorrect Verilog mapping of RTL using increment/decrement operations (++ / --) while indexing into an array on the right-hand side (RHS) of an assignment statement, as described in the attached Customer Notice.
Description of Change:Release of updated Synplify Pro ME version S-2021.09M-SP2 synthesis software bundled with Libero SoC v2022.3 as described in the attached customer notification details.Reason for Change:Release updated Synplify Pro ME version S-2021.09M-SP2 synthesis software bundled with Libero SoC v2022.3 to prevent incorrect VHDL expression evaluation during compilation, when performing subtraction with a real constant number operand, and an additional division/multiplication operation that uses a variable. This is to fix a VHDL compiler issue that occurs in specific VHDL expressions.
Microchip has released a new Datasheet for the ProASIC? 3L Low Power Flash FPGAs with Flash*Freeze Technology of devices. Notification Status: FinalDescription of Change: Updated a note in the ARM? Processor Support in ProASIC 3L FPGAs section.Impacts to Data Sheet: NoneReason for Change: To Improve Productivity.Change Implementation Status: CompleteDate Document Changes Effective: 30 Jan 2023
Part Status:
Available Packaging
Package Qty:
84 per Tray