Shipping Country
Free shipping within the continental US over $50. Conditions apply
Select Country
Manufacturer Part #
A3PN020-1QNG68I
Download the CAD models for this product. Learn more about SnapMagic.
260 per Tray
Shipping Information:
HTS Code:
ECCN:
PCN Information:
Description of Change:Implementation of Inner Box, Reel and MSL Bag Label changes for virtually ALL Microchip products.Reason for Change:To improve productivity by implementing inner box, reel and MSL bag label changes.
Revision History:July 21, 2022: Issued initial notification.June 13, 2023: Issued final notification. Updated the wire material to CuPdAu/2N and die attach material toQMI519 in post change table. Updated table time summary. Revised the affected parts list. Provided estimated first ship date to be on June 15, 2023.Description of Change:Qualification of MTAI as a new assembly site for selected A3P0xx, A3PN0xx, AGL0xxxx and AGLN0xxxx device families available in 68L VQFN (8x8x1mm) and 48L VQFN (6x6x1mm) packages.Reason for Change:To improve manufacturability by qualifying MTAI as a new assembly site.
Description of Change:Release of updated Synplify Pro ME version S-2021.09M-SP2 FPGA synthesis software bundled with Libero SoC v2022.3Reason for Change:Release updated Synplify Pro ME version S-2021.09M-SP2 FPGA synthesis software bundled with Libero SoC v2022.3 to prevent incorrect Verilog mapping of RTL using increment/decrement operations (++ / --) while indexing into an array on the right-hand side (RHS) of an assignment statement, as described in the attached Customer Notice.
Description of Change:Release of updated Synplify Pro ME version S-2021.09M-SP2 synthesis software bundled with Libero SoC v2022.3 as described in the attached customer notification details.Reason for Change:Release updated Synplify Pro ME version S-2021.09M-SP2 synthesis software bundled with Libero SoC v2022.3 to prevent incorrect VHDL expression evaluation during compilation, when performing subtraction with a real constant number operand, and an additional division/multiplication operation that uses a variable. This is to fix a VHDL compiler issue that occurs in specific VHDL expressions.
Part Status:
Inventory held at our manufacturer's warehouse. Subject to availability and transit time.
