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M2S150T-1FCV484M
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Product Category: General Purpose Fpgas, System On Chip FpgasNotification Subject: Data Sheet - IGLOO? 2 FPGA and SmartFusion? 2 SoC FPGA DatasheetDescription of Change:Microchip has released a new Datasheet for the IGLOO? 2 FPGA and SmartFusion? 2 SoC FPGA Datasheet of devices.In the revision F of this document, the Table 3-3 was updated by inserting a note to point out that SmartFusion 2 and IGLOO 2 FPGA Retention Calculator can be obtained through Secure Document Extranet (SDE).Reason for Change: To Improve ProductivityChange Implementation Status: CompleteDate Document Changes Effective: 11 Aug 2026
Microchip has released a new Errata for the SmartFusion?2 Device Errata of devices. If you are using one of these devices please read the document located at SmartFusion?2 Device Errata.Notification Status: FinalDescription of Change: Added 1.25. Avoid eNVM Page Lock and Unlock if Code is Being Executed from eNVM both in Release and Debug ModeImpacts to Data Sheet: NoneReason for Change: To Improve ProductivityChange Implementation Status: CompleteDate Document Changes Effective: 20 Apr 2023NOTE: Please be advised that this is a change to the document only the product has not been changed.
Description of Change:Release of updated Synplify Pro ME version S-2021.09M-SP2 FPGA synthesis software bundled with Libero SoC v2022.3Reason for Change:Release updated Synplify Pro ME version S-2021.09M-SP2 FPGA synthesis software bundled with Libero SoC v2022.3 to prevent incorrect Verilog mapping of RTL using increment/decrement operations (++ / --) while indexing into an array on the right-hand side (RHS) of an assignment statement, as described in the attached Customer Notice.
Description of Change:Release of updated Synplify Pro ME version S-2021.09M-SP2 synthesis software bundled with Libero SoC v2022.3 as described in the attached customer notification details.Reason for Change:Release updated Synplify Pro ME version S-2021.09M-SP2 synthesis software bundled with Libero SoC v2022.3 to prevent incorrect VHDL expression evaluation during compilation, when performing subtraction with a real constant number operand, and an additional division/multiplication operation that uses a variable. This is to fix a VHDL compiler issue that occurs in specific VHDL expressions.
Microchip has released a new Datasheet for the SmartFusion2 Microcontroller Subsystem User Guide of devices.Notification Status: FinalDescription of Change:? Remapping eNVM data from eNVM_1 memory block to Cortex?-M3 Code space is not permitted for SmartFusion? 2 M2S090/150 and IGLOO? 2 M2GL090/150 devices. For information about eNVM remapping and limitation, see the note under Figure 4-28.? Timing models for Fabric to MSS interrupts have been updated with additional time delay. This changes the timing arcs of nets and interface between Fabric to MSS interrupts. For more information about the updated timing arcs, see PCN 17005A.? Updated 1.5.2.3. Embedded Trace Macrocell to include information about timing arcs update from Fabric to Embedded Trace Macrocell.? Updated 10.5.1. SGMII Interface Configuration to include information about timing arcs update from SerDes to Fabric.? Updated 22.3.1. Configuring the FIIC Using the Libero SoC to include information about timing arcs update from Fabric to MSS interrupts.? The document was converted to Microchip template.? The document number was changed to DS50003495 from UG0331.Impacts to Data Sheet: See above details.Reason for Change: To Improve ProductivityChange Implementation Status: CompleteDate Document Changes Effective: 10 Mar 2023
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