STMicroelectronics’ recently introduced STM32H7 high-performance microcontrollers implement the Platform Security Architecture (PSA) from Arm® to provide best-in-class cybersecurity for smart, connected and IoT devices.
Support for the PSA framework is underpinned by the enhanced security features and services offered by the new MCUs.
The introduction of the STM32H7 family comes in response to the demand from device manufacturers for security technology that will safeguard the user’s identity and personal information, and protect physical assets and intellectual property. The PSA running on an STM32H7 MCU helps OEMs to implement state-of-the-art security cost-effffectively in small, resource-constrained devices.
The STM32H7 MCUs integrate hardware- based security features including a true random number generator and advanced cryptographic processor, which simplify the implementation of features to protect embedded applications and global IoT systems against eavesdropping, spoofing or man in-the-middle attacks.
In addition, secure firmware-loading facilities help OEMs to ensure their products can be programmed safely and securely, even off-site at a contract manufacturer or programming house. To enable secure loading, security keys and software services already on the MCU enable OEMs to provide manufacturing partners with encrypted firmware, making it impossible for hackers to intercept, copy or tamper with the code. This process for programming and authenticating the device establishes a root-of-trust so that the device may be securely connected to the end-user’s network and remotely updated over the air throughout the lifetime of the device.
To provide embedded device OEMs with a low-cost platform for secure IoT devices, ST has introduced a new STM32H750 Value Line series of MCUs into its STM32H7 family. It offers the high performance of the Arm® Cortex®-M7 core with double-precision fl oating point unit. Running at up to 400MHz, the STM32H750 MCUs have a 2020 CoreMark® performance rating when executing from Flash memory.
External memory can be used with no performance penalty because of the device’s 32kbyte L1 cache.
