Orders shipping outside of United States will be on hold while the company evaluates tariff impacts.Please contact your salesperson for assistance.
Free shipping within the continental US over $50. Conditions apply
Contribute to the RISC-V ecosystem by hacking on a soft RISC-V core running Linux on a low cost FPGA board.
opens at: Dec 04, 2018 10:00 AM PDT
closes on: Dec 05, 2018 03:00 PM PST
Santa Clara, California
Terra Stone, 5001 Great America Pkwy #350, Santa Clara, CA 95054, USA
Team size allowed: 1 - 2
1st Prize: Visa gift card USD 1000
2nd Prize: Visa gift card USD 500
3rd Prize: Visa gift card USD 250
Exciting Goodie Bags for all participants
Participants will be invited to attend the RISC-V Summit 2018 Expo (Dec 4-5, Santa Clara Convention Center)
RISC-V (pronounced “risk-five”) is a free and open ISA enabling a new era of processor innovation through open standard collaboration. In this Hackathon you are tasked with adding to the RISC-V Linux community. You will be hacking on a soft RISC-V cpu running Linux on the low cost Avalanche FPGA board.
You could implement an application using one of these peripherals, Pmod Ambient Light Sensor or Adafruit Neopixel Shield. Your hack could be a software-based solution which adds to the RISC-V Linux ecosystem, such as a security solution, a unique bootloader or other. Alternatively, you could implement a hardware hack by bringing an Arduino shield, Mikrobus or PMOD peripheral and create a solution.
However, these are just suggestions. You can build anything that could prove to be useful. Eligible participants in this hackathon will be invited to the RISC-V Summit 2018 Expo floor which will be held in the Santa Clara Convention Center on Dec 4-5th.
What’s the Buzz About RISC-V?
Published on Aug 6, 2018 by: Western Digital Corporation
Steffen Hellmold (VP Corporate Strategy) and Martin Fink (EVP & CTO) recently sat down to discuss RISC-V, this first video in the series talks about the “buzz” surrounding RISC-V an View More
Steffen Hellmold (VP Corporate Strategy) and Martin Fink (EVP & CTO) recently sat down to discuss RISC-V, this first video in the series talks about the “buzz” surrounding RISC-V and what an ISA (Instruction Set Architecture) is, why it is needed, and how the open nature of the ISA has the potential to disrupt the processor industry.