Les commandes expédiées à l’extérieur des États-Unis seront en attente pendant que l’entreprise évalue les impacts tarifaires.Veuillez contacter votre vendeur pour obtenir de l’aide.
Livraison gratuite aux États-Unis continentaux à partir de 50 $ US. Des conditions s'appliquent
Référence fabricant
A3PE3000-FGG324
ProASIC3E Series 3000000 System Gate 221 I/O 1.575V Surface Mount FPGA-FPBGA-324
| | |||||||||||
| | |||||||||||
| Nom du fabricant: | Microchip | ||||||||||
| Emballage standard: | Product Variant Information section Emballages disponiblesQté d'emballage(s) :84 par Tray | ||||||||||
| Code de date: | |||||||||||
Microchip A3PE3000-FGG324 - Spécifications du produit
Informations de livraison:
ECCN:
Informations PCN:
PCN Status:Final NotificationDescription of Change:Release of updated software version of Synplify Pro Microchip Edition v2023.09M-1 & Synplify Pro Standalone v2023.09-1 for various FPGA devices.Reason for Change:Synplify Pro standalone all-vendor versions 2023.03 and 2023.09, as well as Microchip Edition version 2023.09M could incorrectly extract the enable signal logic during RTL synthesis when the signal path contains a set of multiplexors connected in series around a register, and the MUXs are driven by bus ports. This is described in the attached Customer Notice.
Description of Change:Release of updated Synplify Pro ME version S-2021.09M-SP2 FPGA synthesis software bundled with Libero SoC v2022.3Reason for Change:Release updated Synplify Pro ME version S-2021.09M-SP2 FPGA synthesis software bundled with Libero SoC v2022.3 to prevent incorrect Verilog mapping of RTL using increment/decrement operations (++ / --) while indexing into an array on the right-hand side (RHS) of an assignment statement, as described in the attached Customer Notice.
Description of Change:Release of updated Synplify Pro ME version S-2021.09M-SP2 synthesis software bundled with Libero SoC v2022.3 as described in the attached customer notification details.Reason for Change:Release updated Synplify Pro ME version S-2021.09M-SP2 synthesis software bundled with Libero SoC v2022.3 to prevent incorrect VHDL expression evaluation during compilation, when performing subtraction with a real constant number operand, and an additional division/multiplication operation that uses a variable. This is to fix a VHDL compiler issue that occurs in specific VHDL expressions.
Statut du produit:
- https://futureelec.wufoo.com/forms/?formname=r8bzou01ws8brs&field12=NA&field16=fr&field2=A3PE3000-FGG324&field4=Microchip&field18=https://p1na.futureelectronics.com/fr/es/p/semiconductors--programmable-logic--fpga-flash/a3pe3000-fgg324-microchip-7062756
- https://futureelec.wufoo.com/forms/?formname=r8bzou01ws8brs&field12=NA&field16=fr&field2=A3PE3000-FGG324&field4=Microchip&field18=https://p1na.futureelectronics.com/fr/es/p/semiconductors--programmable-logic--fpga-flash/a3pe3000-fgg324-microchip-7062756
Emballages disponibles
Qté d'emballage(s) :
84 par Tray