Lattice Semiconductor MachXO5-NX Advanced Secure Control FPGA
Higher Density, More Memory for Complex Control Applications, Fast and Proven I/O Capabilities, Intellectual Property Protection
The Lattice Semiconductor MachXO5™-NX family is built on their Nexus FPGA platform, using low-power 28 nm FD-SOI technology. It combines the extreme flexibility of an FPGA with the low power and high reliability (due to the extreme low Soft Error Rate) of FD-SOI technology, and offers small footprint package options.
The MachXO5-NX family supports a variety of interfaces including MIPI D-PHY (CSI-2, DSI), LVDS, SLVS, subLVDS, SGMII (Gigabit Ethernet), and more. The FPGA includes embedded flash memory for on-chip multi-boot and UFM.
Processing features of the first MachXO5-NX device include 25k logic cells, 20 18 × 18 multipliers, 1.9 Mb of embedded memory (consisting of EBR and LRAM blocks), distributed memory, DRAM interfaces (supporting DDR3, DDR3L, LPDDR2, and LPDDR3 up to 1066 Mbps × 16 data width).
The MachXO5-NX FPGA supports the fast configuration of its reconfigurable SRAM-based logic fabric, and ultra-fast configuration of its programmable sysI/O™ from on-chip Flash.
To secure user designs, the MachXO5-NX security features include bitstream encryption, authentication, and password protection. In addition to the high reliability inherent to FD-SOI technology (due to its extreme low SER), active reliability features such as built-in frame-based SED/SEC (for SRAM-based logic fabric), and ECC (for EBR and LRAM) are also supported. Built-in ADC is available in each device for system monitoring functions.
Lattice Radiant™ design software allows large complex user designs to be efficiently implemented on the MachXO5-NX FPGA family. Synthesis library support for MachXO5-NX devices is available for popular logic synthesis tools. Radiant tools use the synthesis tool output along with constraints from its floor planning tools, to place and route the user design in MachXO5-NX device. The tools extract timing from the routing, and back-annotate it into the design for timing verification.
Lattice Semiconductor provides many pre-engineered Intellectual Property (IP) modules for the MachXO5-NX family. By using these configurable soft IP cores as standardized blocks, you are free to concentrate on the unique aspects of your design, increasing your productivity.
LVDS Tunneling Protocol & Interface (LTPI) in Datacenter-ready Secure Control Module
MachXO5™- NX Development Board
Prototyping Board with Configurable I/O, SGMII, and ADC Interface
The MachXO5-NX Development Board features the MachXO5-NX-25 in a 400-ball caBGA package. This device offers a variety of features and programmability that enhances Secure Control PLD functionality with multiple boot capabilities. Its cryptographic engine supports user-mode security features. Alongside the cryptographic engine, numerous system functions are included such as two PLLs and 432 kbits of embedded RAM plus hardened implementations of I2C and SPI. Flexible, high performance I/O support numerous single-ended and differential standards including LVDS and MIPI.
MachXO5-NX Development Board Quick Start Guide