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Référence fabricant
AGL250V2-CSG196I
AGL250 Series 250000 System Gates 143 I/O IGLOO Low Power Flash FPGA - CSP-196
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| Nom du fabricant: | Microchip | ||||||||||
| Emballage standard: | Product Variant Information section Emballages disponiblesQté d'emballage(s) :348 par Tray Style d'emballage :CSP-196 Méthode de montage :Surface Mount | ||||||||||
| Code de date: | |||||||||||
Microchip AGL250V2-CSG196I - Spécifications du produit
Informations de livraison:
ECCN:
Informations PCN:
PCN Status:Final NotificationDescription of Change:Release of updated software version of Synplify Pro Microchip Edition v2023.09M-1 & Synplify Pro Standalone v2023.09-1 for various FPGA devices.Reason for Change:Synplify Pro standalone all-vendor versions 2023.03 and 2023.09, as well as Microchip Edition version 2023.09M could incorrectly extract the enable signal logic during RTL synthesis when the signal path contains a set of multiplexors connected in series around a register, and the MUXs are driven by bus ports. This is described in the attached Customer Notice.
Description of Change:Release of updated Synplify Pro ME version S-2021.09M-SP2 FPGA synthesis software bundled with Libero SoC v2022.3Reason for Change:Release updated Synplify Pro ME version S-2021.09M-SP2 FPGA synthesis software bundled with Libero SoC v2022.3 to prevent incorrect Verilog mapping of RTL using increment/decrement operations (++ / --) while indexing into an array on the right-hand side (RHS) of an assignment statement, as described in the attached Customer Notice.
Description of Change:Release of updated Synplify Pro ME version S-2021.09M-SP2 synthesis software bundled with Libero SoC v2022.3 as described in the attached customer notification details.Reason for Change:Release updated Synplify Pro ME version S-2021.09M-SP2 synthesis software bundled with Libero SoC v2022.3 to prevent incorrect VHDL expression evaluation during compilation, when performing subtraction with a real constant number operand, and an additional division/multiplication operation that uses a variable. This is to fix a VHDL compiler issue that occurs in specific VHDL expressions.
Statut du produit:
Microchip AGL250V2-CSG196I - Caractéristiques techniques
| System Gates: | 250000 |
| No of I/O Lines: | 143 |
| Operating Frequency-Max: | 160MHz |
| Flash Size (Bits): | 1kb |
| RAM Size (Bits): | 36kb |
| Supply Voltage: | 1.14V to 1.575V |
| Operating Temp Range: | -40°C to +100°C |
| Storage Temperature Range: | -65°C to +150°C |
| Interface Type: | Jtag |
| Temperature Grade: | Industrial |
| Moisture Sensitivity Level: | 3 |
| Style d'emballage : | CSP-196 |
| Méthode de montage : | Surface Mount |
Emballages disponibles
Qté d'emballage(s) :
348 par Tray
Style d'emballage :
CSP-196
Méthode de montage :
Surface Mount