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Manufacturer Part #


MC100EP142 Series 3.3 V / 5 V 2.8 GHz ECL 9−Bit Shift Register - LQFP-32

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Mfr. Name: ON Semiconductor
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Product Specification Section
Technical Attributes
Attributes Table
Input Voltage-Max: 2415mV
Temperature Range: -40°C to +85°C
Supply Voltage-Nom: 3V to 5.5V
Frequency-Max: 2.8GHz
Package Style:  LQFP-32
Mounting Method: Surface Mount
Features & Applications

The MC100EP142 is a 9−bit shift register, designed with byte-parity applications in mind. The MC100EP142 is capable of performing serial/parallel data into serial/parallel out and shifting in only one direction. The nine inputs D0 − D8 accept parallel input data, while S−IN accepts serial input data. The QT0:87 outputs do not need to be terminated for the shift operation to function. To minimize power, any Q output not used should be left unterminated.

The SEL (Select) input pin is used to switch between the two modes of operation − SHIFT and LOAD. The shift direction is from Bit 0 to Bit 8. Input data is accepted by the registers a set−up time before the positive going edge of CLK0 or CLK1; shifting is also accomplished on the positive clock edge. A HIGH on the Master Reset pin (MR) asynchronously resets all the registers to zero, overriding CLK0 and CLK1 inputs. The 100 Series contains temperature compensation.

Key Features:

  • Shift Frequency >2.8 GHz (Typical)
  • 9-Bit for Byte−Parity Applications
  • Asynchronous Master Reset
  • Dual Clocks
  • PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V
  • NECL Mode Operating Range: VCC = 0 V with VEE = −3.0 V to −5.5 V
  • Open Input Default State
  • Safety Clamp on Inputs
  • Pb−Free Packages are Available


  • Byte Parity
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Factory Lead Time:
14 Weeks
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