onsemi | MC100EP142FAG

The MC100EP142 is a 9−bit shift register, designed with byte-parity applications in mind. The MC100EP142 is capable of performing serial/parallel data into serial/parallel out and shifting in only one direction. The nine inputs D0 − D8 accept parallel input data, while S−IN accepts serial input data. The QT0:87 outputs do not need to be terminated for the shift operation to function. To minimize power, any Q output not used should be left unterminated.

The SEL (Select) input pin is used to switch between the two modes of operation − SHIFT and LOAD. The shift direction is from Bit 0 to Bit 8. Input data is accepted by the registers a set−up time before the positive going edge of CLK0 or CLK1; shifting is also accomplished on the positive clock edge. A HIGH on the Master Reset pin (MR) asynchronously resets all the registers to zero, overriding CLK0 and CLK1 inputs. The 100 Series contains temperature compensation.

Key Features:

• Shift Frequency >2.8 GHz (Typical)
• 9-Bit for Byte−Parity Applications
• Asynchronous Master Reset
• Dual Clocks
• PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V
• NECL Mode Operating Range: VCC = 0 V with VEE = −3.0 V to −5.5 V
• Open Input Default State
• Safety Clamp on Inputs
• Pb−Free Packages are Available

Applications:

• Byte Parity